Computer NetworksDigital Transmission

Multilevel Coding

LevelIntermediate

Duration90 mins

TopicDigital Transmission

3 / 5

4B/5B Block Encoding

The Hidden Challenge of Digital Communication

Digital communication systems face a fundamental paradox: to correctly interpret a stream of bits, the receiver must know precisely when each bit begins and ends—yet this timing information must somehow be embedded within the data itself. Without a separate clock signal (impractical for most applications), the receiver must extract timing from the data stream's transitions.

This creates an immediate problem: what happens when the data contains long sequences of identical bits? Consider the binary sequence 00000000 00000000: an NRZ signal would remain at a constant voltage for 16 bit periods. The receiver's clock, with its inherent drift, could easily slip by one or more bit positions, causing catastrophic synchronization failure.

4B/5B encoding emerged as an elegant solution to this problem. By mapping every 4-bit data nibble to a carefully selected 5-bit code word, 4B/5B guarantees that no transmitted sequence contains more than three consecutive zeros—ensuring adequate transitions for reliable clock recovery while imposing only 25% overhead (far less than Manchester's 100%).

What You Will Master

By completing this page, you will understand the complete theory and implementation of 4B/5B encoding: the mathematical constraints that govern code design, the complete code table, special control symbols, DC balance properties, error detection capabilities, and its critical role in Fast Ethernet and FDDI. You'll gain the depth expected of a networking professional who understands physical layer design.

Block Coding Principles and 4B/5B Design

Block coding transforms data by mapping fixed-size groups (blocks) of input bits to larger groups of output bits. The extra bits—the redundancy—enable the encoding to satisfy constraints that raw data cannot guarantee.

The mB/nB Framework

In the general notation mB/nB:

m = number of input data bits
n = number of output code bits (n > m)
Efficiency = m/n × 100%

For 4B/5B:

m = 4 input bits (16 possible combinations)
n = 5 output bits (32 possible combinations)
Efficiency = 4/5 = 80%

Why 4B/5B?

Design Goals:

Maximum Run Length Constraint: No more than 3 consecutive zeros in any valid output sequence
Reasonable Efficiency: At least 80% (only 25% overhead)
Unique Decodability: Each 4-bit input maps to exactly one 5-bit output
Control Symbols: Reserve some 5-bit patterns for special functions
DC Balance Tendency: Minimize DC component for transformer-coupled links

The Mathematical Constraint:

To guarantee no more than 3 consecutive zeros across code word boundaries, each code word must satisfy:

No more than 1 leading zero (one zero at the start)
No more than 2 trailing zeros (two zeros at the end)

Why? Because if code word A ends with 2 zeros and code word B starts with 1 zero, the concatenation AB has 2 + 1 = 3 consecutive zeros—our maximum allowed.

The Concatenation Constraint

When designing block codes, you must consider not just individual code words, but all possible concatenations. A code word that looks fine in isolation (like 00110) might create run-length violations when followed by certain other code words. 4B/5B's leading/trailing zero constraint elegantly handles all possible combinations.

Counting Valid Code Words

How many 5-bit patterns satisfy our constraints? Let's enumerate:

5-bit patterns = 32 total

Invalid patterns (more than 1 leading zero):

00xxx: 8 patterns (but 01xxx are valid, so 00xxx = 8 invalid)

Invalid patterns (more than 2 trailing zeros):

xxx000: 4 patterns
But 00000 already counted above
Additional invalid: x1000, x0000 where x ≠ 0... (complex counting)

Direct count of valid patterns: Patterns with 0 leading zeros: 1xxxx (16 patterns) Patterns with 1 leading zero: 01xxx (8 patterns) Total first-constraint compliant: 24 patterns

From these, eliminate trailing-zero violations:

10000 (3 trailing zeros) ✗
01000 (3 trailing zeros) ✗
11000 (3 trailing zeros) ✗
etc.

Result: 23 valid code words

Of these:

16 are used for data (hex 0-F)
7 are available for control symbols
9 remaining 5-bit patterns are invalid

4B/5B Code Table - Data Symbols
Data (Hex)	Data (Binary)	4B/5B Code	of 1s	Notes
0	0000	11110	4	High transition density
1	0001	01001	2	Valid: 1 leading zero
2	0010	10100	2	Balanced
3	0011	10101	3	Balanced
4	0100	01010	2	Valid: 1 leading zero
5	0101	01011	3	Valid: 1 leading zero
6	0110	01110	3	Valid: 1 leading zero
7	0111	01111	4	Valid: 1 leading zero
8	1000	10010	2	Balanced
9	1001	10011	3	Balanced
A	1010	10110	3	Balanced
B	1011	10111	4	Balanced
C	1100	11010	3	Balanced
D	1101	11011	4	Balanced
E	1110	11100	3	2 trailing zeros (max)
F	1111	11101	4	Balanced

Control Symbols and Link Management

Beyond the 16 data symbols, 4B/5B reserves additional code words for link control functions. These control symbols manage frame boundaries, link status, and error conditions—essential functions that would otherwise require out-of-band signaling.

Control Symbol Definitions

4B/5B Control Symbols
Symbol	4B/5B Code	Function	Usage Context
I (Idle)	11111	Link Idle	Transmitted between frames to maintain synchronization
J (Start 1)	11000	Start of Frame (1st)	First symbol of preamble, used with K
K (Start 2)	10001	Start of Frame (2nd)	Second symbol of preamble, follows J
T (Terminate)	01101	End of Frame	Marks end of data in frame
R (Reserved)	00111	Reserved/Reset	Link reset or reserved for future use
S (Set)	11001	Reserved	Reserved for future use
H (Halt)	00100	Halt	Signals intentional halt (FDDI)

Frame Delimiting

The J-K Start Delimiter:

Frame transmission begins with the J-K symbol pair:

J = 11000 (violates normal code: would be invalid if not special)
K = 10001 (unique pattern)

The J-K combination:

Creates a unique bit pattern not found in data (11000 10001)
Signals unambiguous frame start
Provides additional synchronization reference
Cannot occur within valid data (J is not a data code)

The T Terminator:

Frames end with the T symbol (01101):

Signals end of data payload
Receiver knows to expect idle or new frame
Enables immediate turnaround in half-duplex

Idle Pattern and Link Maintenance

Continuous Idle Transmission:

Between frames, the transmitter continuously sends Idle symbols (11111):

Frame 1 [T] I I I I I I I I I I I [J K] Frame 2
                ↑
         Idle fill maintains clock lock

Why not just keep the line quiet?

Clock Maintenance: Receiver PLL needs transitions to stay locked
Link Status: Idle = link is up and functional
Activity Detection: Distinguishes active idle from cable disconnect
DC Balance: Idle pattern (11111) helps maintain DC equilibrium

Note on I Symbol: The Idle symbol (11111) has five 1s, seemingly violating our "no long runs" rule. However, when combined with MLT-3 encoding:

Each '1' causes a transition in MLT-3
11111 produces maximum transitions (excellent for clock recovery)
The concern was runs of zeros, not ones

Invalid Code Detection

Of the 32 possible 5-bit patterns, 9 are invalid (not assigned to data or control). If a receiver detects an invalid code, it indicates a transmission error. This provides basic error detection capability at the physical layer—before CRC checking occurs at the data link layer.

Control Symbol Functions

•Frame Delimiting: J-K start delimiter and T terminator mark frame boundaries unambiguously
•Link Idle: I symbol transmitted between frames maintains clock synchronization
•Error Detection: Invalid codes (9 of 32 patterns) signal physical layer errors
•Special Actions: H, R, S symbols support link management functions
•Unambiguous Decoding: Control symbols cannot be confused with any data pattern

DC Balance, Running Disparity, and Spectral Properties

One limitation of 4B/5B is that it does not intrinsically guarantee DC balance. Understanding this limitation—and how systems work around it—reveals important principles of physical layer design.

The DC Balance Challenge

What is DC Balance?

A DC-balanced signal has equal energy in positive and negative excursions over time, resulting in a zero average voltage. DC balance is critical for:

Transformer Coupling: Transformers block DC; imbalanced signals cause baseline wander
AC-Coupled Links: Capacitors in the signal path block DC components
EMI Reduction: Balanced signals produce less electromagnetic interference

4B/5B's DC Imbalance:

Examine the code table:

Data	4B/5B Code	# of 1s	Disparity
0	11110	4	+4
1	01001	2	+2
...	...	...	...
F	11101	4	+4

Most codes have more 1s than 0s (disparity > 0). Random data will tend to produce more 1s than 0s, creating a DC offset.

How Systems Compensate

MLT-3 Encoding (Fast Ethernet):

4B/5B's DC imbalance is partially mitigated by MLT-3:

MLT-3 signal cycles: 0 → +V → 0 → -V → 0
Over time, positive and negative excursions tend to balance
The combination (4B/5B + MLT-3) is approximately DC-balanced for random data

Scrambling:

Fast Ethernet (100BASE-TX) adds a scrambler after 4B/5B encoding:

Polynomial: x¹¹ + x⁹ + 1
Randomizes the bit pattern
Distributes spectral energy
Improves DC balance for worst-case data patterns
Reduces pattern-dependent EMI

4b5b_dc_analysis.py
Python
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
class Encoder4B5B:
    """
    4B/5B Block Encoder with DC Balance Analysis
    
    Implements the standard 4B/5B encoding used in Fast Ethernet
    and FDDI, with analysis tools for understanding DC characteristics.
    """
    
    # Standard 4B/5B code table
    DATA_CODES = {
        0x0: 0b11110,  # 0000 -> 11110
        0x1: 0b01001,  # 0001 -> 01001
        0x2: 0b10100,  # 0010 -> 10100
        0x3: 0b10101,  # 0011 -> 10101
        0x4: 0b01010,  # 0100 -> 01010
        0x5: 0b01011,  # 0101 -> 01011
        0x6: 0b01110,  # 0110 -> 01110
        0x7: 0b01111,  # 0111 -> 01111
        0x8: 0b10010,  # 1000 -> 10010
        0x9: 0b10011,  # 1001 -> 10011
        0xA: 0b10110,  # 1010 -> 10110
        0xB: 0b10111,  # 1011 -> 10111
        0xC: 0b11010,  # 1100 -> 11010
        0xD: 0b11011,  # 1101 -> 11011
        0xE: 0b11100,  # 1110 -> 11100
        0xF: 0b11101,  # 1111 -> 11101
    }
    
    # Control symbols
    CONTROL_CODES = {
        'I': 0b11111,  # Idle
        'J': 0b11000,  # Start-of-frame 1
        'K': 0b10001,  # Start-of-frame 2
        'T': 0b01101,  # End-of-frame
        'R': 0b00111,  # Reset
        'S': 0b11001,  # Set (reserved)
        'H': 0b00100,  # Halt
    }
    
    # Invalid codes (can be used for error detection)
    INVALID_CODES = [
        0b00000, 0b00001, 0b00010, 0b00011,
        0b00101, 0b00110, 0b01000, 0b10000, 0b11111
    ]
    
    def encode_nibble(self, nibble: int) -> int:
        """Encode a 4-bit nibble to 5-bit code."""
        if nibble not in self.DATA_CODES:
            raise ValueError(f"Invalid nibble: {nibble}")
        return self.DATA_CODES[nibble]
    
    def encode_byte(self, byte: int) -> tuple[int, int]:
        """Encode a byte as two 5-bit codes (high nibble first)."""
        high = (byte >> 4) & 0xF
        low = byte & 0xF
        return (self.encode_nibble(high), self.encode_nibble(low))
    
    def encode_data(self, data: bytes) -> list[int]:
        """Encode byte array to list of 5-bit codes."""
        codes = []
        for byte in data:
            high, low = self.encode_byte(byte)
            codes.extend([high, low])
        return codes
    
    def calculate_disparity(self, code: int, bits: int = 5) -> int:
        """
        Calculate running disparity contribution.
        
        Disparity = (number of 1s) - (number of 0s)
        Positive disparity means more 1s than 0s.
        """
        ones = bin(code).count('1')
        zeros = bits - ones
        return ones - zeros
    
    def analyze_dc_balance(self, codes: list[int]) -> dict:
        """
        Analyze DC balance of encoded stream.
        
        Returns statistics on running disparity and DC offset tendency.
        """
        running_disparity = 0
        max_disparity = 0
        min_disparity = 0
        disparity_history = []
        
        for code in codes:
            disp = self.calculate_disparity(code)
            running_disparity += disp
            max_disparity = max(max_disparity, running_disparity)
            min_disparity = min(min_disparity, running_disparity)
            disparity_history.append(running_disparity)
        
        total_bits = len(codes) * 5
        avg_disparity = running_disparity / len(codes) if codes else 0
        
        return {
            "total_codes": len(codes),
            "total_bits": total_bits,
            "final_disparity": running_disparity,
            "max_disparity": max_disparity,
            "min_disparity": min_disparity,
            "avg_disparity_per_code": avg_disparity,
            "dc_offset_estimate": running_disparity / total_bits if total_bits else 0,
            "disparity_history": disparity_history
        }
    
    def check_run_length(self, codes: list[int]) -> dict:
        """
        Verify that encoded stream satisfies run-length constraints.
        
        4B/5B guarantees no more than 3 consecutive zeros.
        """
        # Convert to bit stream
        bits = []
        for code in codes:
            for i in range(4, -1, -1):
                bits.append((code >> i) & 1)
        
        max_zeros = 0
        current_zeros = 0
        
        for bit in bits:
            if bit == 0:
                current_zeros += 1
                max_zeros = max(max_zeros, current_zeros)
            else:
                current_zeros = 0
        
        return {
            "max_consecutive_zeros": max_zeros,
            "constraint_satisfied": max_zeros <= 3,
            "total_bits": len(bits)
        }
 
 
# Demonstration
if __name__ == "__main__":
    encoder = Encoder4B5B()
    
    # Encode sample data
    sample_data = bytes([0x00, 0xFF, 0xA5, 0x5A, 0x12, 0x34])
    print("4B/5B Encoding Analysis")
    print("=" * 60)
    print(f"Input data: {sample_data.hex().upper()}")
    
    codes = encoder.encode_data(sample_data)
    print(f"Encoded: {[format(c, '05b') for c in codes]}")
    
    # DC balance analysis
    dc_analysis = encoder.analyze_dc_balance(codes)
    print(f"\nDC Balance Analysis:")
    for key, value in dc_analysis.items():
        if key != "disparity_history":
            print(f"  {key}: {value}")
    
    # Run length check
    run_analysis = encoder.check_run_length(codes)
    print(f"\nRun Length Analysis:")
    for key, value in run_analysis.items():
        print(f"  {key}: {value}")

Comparison with DC-Balanced Codes

8B/10B (Gigabit Ethernet, Fibre Channel):

8B/10B provides guaranteed DC balance through running disparity control:

Property	4B/5B	8B/10B
Efficiency	80%	80%
DC Balance	Not guaranteed	Guaranteed
Max Run Length	3 zeros	5 identical
Control Symbols	7	12 K-codes
Complexity	Low	Medium
Used In	Fast Ethernet, FDDI	Gigabit Ethernet, FC

8B/10B Running Disparity:

Each 10-bit code comes in two versions: positive and negative disparity
Encoder alternates between versions to maintain running disparity near zero
Guarantees DC balance regardless of data pattern

4B/5B's lack of guaranteed DC balance is acceptable for Fast Ethernet because:

MLT-3 encoding provides inherent balance tendency
Scrambling randomizes patterns
Short cable runs (100m max) tolerate some baseline wander
Lower complexity reduces cost and power

The Complexity Trade-off

4B/5B was designed in the 1980s when chip complexity was expensive. Its simplicity—a single lookup table—made it practical for high-volume, low-cost implementations. 8B/10B's disparity tracking required more logic but delivered better signal quality, reflecting the different constraints of Gigabit-era design.

4B/5B in Fast Ethernet (100BASE-TX)

The combination of 4B/5B with MLT-3 in 100BASE-TX represents a masterful engineering compromise—achieving 100 Mbps over Category 5 cable with technology that was manufacturable at scale in the mid-1990s.

The Complete 100BASE-TX Signal Chain

Transmission Path:

[MII] → [4B/5B Encoder] → [Scrambler] → [NRZ-I] → [MLT-3] → [Line Driver] → Cable
  ↓           ↓              ↓           ↓          ↓
4-bit      5-bit         Randomized   Binary    3-level
nibbles    codes         stream       stream    analog

Rate Expansion:

MII (Media Independent Interface): 25 MHz × 4 bits = 100 Mbps
4B/5B output: 25 MHz × 5 bits = 125 Mbps = 125 Mbaud
MLT-3 fundamental: 125 Mbaud / 4 = 31.25 MHz

Stage-by-Stage Analysis

1. MII Interface: The MAC sends data to the PHY in 4-bit nibbles at 25 MHz via the standard MII bus. This interface abstracts the physical layer, allowing different PHY types (100BASE-TX, 100BASE-FX, etc.) to connect to the same MAC.

2. 4B/5B Encoding: Each 4-bit nibble is looked up in the code table, producing a 5-bit symbol. The encoder operates at 25 million nibbles/second, outputting 125 million bits/second.

3. Scrambling (NRZI Stream Cipher): The scrambler uses polynomial x¹¹ + x⁹ + 1:

scrambled_bit[n] = data_bit[n] XOR scrambled_bit[n-9] XOR scrambled_bit[n-11]

Scrambling provides:

Spectral whitening (spreads energy across frequencies)
Pattern randomization (breaks up repetitive data)
Improved DC balance (randomizes 1s and 0s)
EMI reduction (prevents discrete spectral lines)

4. NRZ-I Conversion: The scrambled stream is converted to NRZ-I (Non-Return to Zero Inverted):

'1' = transition (change state)
'0' = no transition (maintain state)

This intermediate step simplifies the MLT-3 implementation.

5. MLT-3 Encoding: The NRZ-I stream drives the MLT-3 state machine:

Transition: cycle through 0 → +V → 0 → -V → 0
No transition: maintain current level

6. Line Driving: The analog output driver delivers ±1V differential into the 100Ω cable impedance, with pre-emphasis to compensate for cable losses.

Converting Mermaid diagram...

Frame Structure with 4B/5B

Idle and Preamble:

...I I I I J K [SFD] [Dest MAC] [Src MAC] [Type/Len] [Data...] [FCS] T R...
           ↑   ↑
     Start  Preamble/SFD encoded as 4B/5B data symbols
     Delim

Inter-Packet Gap:

Minimum 96 bit times (960 ns at 100 Mbps)
Transmitted as Idle symbols (at least 12 Idles after T)
Allows receiver to process previous frame

Start of Frame:

J-K symbol pair (11000 10001)
Followed by preamble and SFD encoded as hex 55...5D
Receiver uses J-K to achieve precise symbol synchronization

End of Frame:

T symbol (01101) marks end of data
R symbols may follow for padding
Then continuous Idle until next frame

100BASE-TX Timing Specifications
Parameter	Value	Derivation
Data Rate	100 Mbps	User payload rate
4B/5B Symbol Rate	25 Msymbols/s	100 Mbps / 4 bits
Line Rate	125 Mbaud	25M × 5 bits
Symbol Period	8 ns	1 / 125M
Max Frequency (MLT-3)	31.25 MHz	125M / 4
Inter-Packet Gap	0.96 µs	96 bits at 100 Mbps
Max Cable Length	100 m	Signal integrity limit

Common Implementation Errors

The most common 4B/5B implementation errors involve incorrect handling of control symbols. The J-K start delimiter must be transmitted exactly at frame start—not earlier (which breaks inter-packet timing) or later (which corrupts preamble). Similarly, the T terminator must immediately follow the FCS—missing or duplicated terminators cause frame parsing failures.

4B/5B in FDDI and Beyond

Before Fast Ethernet adopted 4B/5B, the encoding scheme was developed for FDDI (Fiber Distributed Data Interface)—a 100 Mbps token-passing ring network that pioneered many of the physical layer techniques later used in Ethernet.

FDDI: The Original 4B/5B Application

FDDI Overview:

Standard: ANSI X3T9.5, ISO 9314
Topology: Dual counter-rotating rings
Speed: 100 Mbps
Media: Multimode fiber (62.5/125 µm) or STP cable
Encoding: 4B/5B + NRZI (not MLT-3)

Why 4B/5B for FDDI?

FDDI required:

100 Mbps throughput: Matched contemporary mainframe I/O speeds
Long distances: Up to 2 km between nodes, 100 km total ring circumference
Reliable clocking: Token-ring timing is critical
Cost-effective PHY: Silicon of the 1980s had limited complexity

4B/5B delivered efficient encoding suitable for fiber optic transmission where DC balance was less critical (fiber uses intensity modulation).

FDDI Physical Layer Differences

FDDI vs 100BASE-TX:

Aspect	FDDI	100BASE-TX
Line Coding	NRZI	MLT-3
Media	Fiber / STP	UTP
Distance	2 km	100 m
Wavelength	1300 nm	N/A (electrical)
Topology	Ring	Star

NRZI in FDDI: FDDI uses NRZI (Non-Return to Zero Inverted) directly on fiber:

'1' = light transition (on→off or off→on)
'0' = no transition
4B/5B ensures enough transitions for clock recovery

Unlike electrical transmission, fiber doesn't have DC balance issues (you're modulating light intensity, not voltage). This simplified the FDDI design compared to 100BASE-TX's MLT-3 requirement.

FDDI Control Symbols

•Q (Quiet): 00000 - Line quiet (no signal)
•I (Idle): 11111 - Link idle, clock maintenance
•H (Halt): 00100 - Halt symbol for ring management
•J (Start 1): 11000 - First symbol of starting delimiter
•K (Start 2): 10001 - Second symbol of starting delimiter
•T (Terminate): 01101 - End of frame marker
•S (Set): 11001 - Reserved for SET operations

Other 4B/5B Applications

100BASE-FX (Fiber Fast Ethernet):

Uses 4B/5B + NRZI (like FDDI)
Multimode fiber, 1300 nm
2 km range (half-duplex), 412 m (full-duplex, timing constrained)
Popular in industrial and campus backbones

100VG-AnyLAN:

Competing standard to 100BASE-TX (lost the market)
Used 5B/6B encoding (different approach)
Demand-priority access instead of CSMA/CD

The Legacy of 4B/5B

4B/5B established principles that influenced all subsequent high-speed encoding:

Block Coding Concept: Map m-bit data to n-bit codes with guaranteed properties
Transition Density: Ensure enough edges for clock recovery
Control Symbols: Reserve codes for in-band signaling
Error Detection: Invalid codes indicate physical layer errors

These concepts evolved into:

8B/10B: Added DC balance (used in Gigabit Ethernet, Fibre Channel)
64B/66B: Higher efficiency for 10 Gigabit and beyond
128B/130B: Used in PCIe Gen 3+

Why FDDI Lost to Fast Ethernet

Despite FDDI's technical elegance and earlier introduction, Fast Ethernet won the market because it used existing Category 5 UTP cabling (already installed for 10BASE-T), cost less (no fiber connectors), and fit into the familiar Ethernet architecture. FDDI required new fiber infrastructure and expensive concentrators. Technology alone rarely wins—economics and compatibility matter too.

Summary: Mastering 4B/5B Encoding

4B/5B encoding represents a fundamental technique in digital communications—the art of adding just enough redundancy to guarantee desired signal properties while minimizing overhead. Let's consolidate the essential knowledge:

Core Concepts to Remember

•Block Code Structure: 4-bit input nibbles map to 5-bit output codes via a fixed lookup table
•Run-Length Constraint: Maximum 3 consecutive zeros guaranteed (1 leading + 2 trailing zero limit)
•25% Overhead: Efficiency = 80% (5/4 expansion), much better than Manchester's 50%
•Control Symbols: J-K (start), T (terminate), I (idle) manage frame boundaries and link maintenance
•Error Detection: 9 invalid codes signal physical layer errors before CRC checking
•MLT-3 Synergy: Combined with MLT-3, enables 100 Mbps over Category 5 UTP at 31.25 MHz

4B/5B Quick Reference Card
Parameter	Value	Notes
Code Rate	4:5	4 data bits → 5 code bits
Efficiency	80%	Higher than Manchester (50%)
Max Run	3 zeros	Guaranteed by code design
Data Codes	16	Hex 0-F
Control Codes	7	I, J, K, T, R, S, H
Invalid Codes	9	Error detection capability
Primary Use	100BASE-TX, FDDI	Combined with MLT-3 or NRZI

4B/5B Advantages

•Simple lookup table implementation
•Guaranteed transition density
•Low overhead (only 25%)
•Built-in control symbols
•Physical layer error detection
•Proven in billions of devices

4B/5B Limitations

•No guaranteed DC balance
•Requires scrambling for EMI compliance
•Not self-clocking (needs additional encoding)
•Limited to moderate speeds
•Fixed code (no rate adaptation)
•Superseded by 8B/10B for higher speeds

Looking Ahead:

With 4B/5B mastered, you're ready to explore its successor: 8B/10B encoding. This more sophisticated scheme solves 4B/5B's DC balance limitation through running disparity control, enabling higher data rates and longer cable runs. 8B/10B became the foundation for Gigabit Ethernet, Fibre Channel, and numerous other high-speed interfaces.

Page Complete

You now possess a comprehensive understanding of 4B/5B block encoding—from its mathematical foundations through its implementation in Fast Ethernet and FDDI. This knowledge is essential for understanding all modern block coding schemes that built upon 4B/5B's pioneering design.

3 / 5

Loading learning content...

Computer NetworksDigital Transmission

Multilevel Coding

LevelIntermediate

Duration90 mins

TopicDigital Transmission

3 / 5

4B/5B Block Encoding

The Hidden Challenge of Digital Communication

What You Will Master

Block Coding Principles and 4B/5B Design

The mB/nB Framework

In the general notation mB/nB:

m = number of input data bits
n = number of output code bits (n > m)
Efficiency = m/n × 100%

For 4B/5B:

m = 4 input bits (16 possible combinations)
n = 5 output bits (32 possible combinations)
Efficiency = 4/5 = 80%

Why 4B/5B?

Design Goals:

Maximum Run Length Constraint: No more than 3 consecutive zeros in any valid output sequence
Reasonable Efficiency: At least 80% (only 25% overhead)
Unique Decodability: Each 4-bit input maps to exactly one 5-bit output
Control Symbols: Reserve some 5-bit patterns for special functions
DC Balance Tendency: Minimize DC component for transformer-coupled links

The Mathematical Constraint:

To guarantee no more than 3 consecutive zeros across code word boundaries, each code word must satisfy:

No more than 1 leading zero (one zero at the start)
No more than 2 trailing zeros (two zeros at the end)

Why? Because if code word A ends with 2 zeros and code word B starts with 1 zero, the concatenation AB has 2 + 1 = 3 consecutive zeros—our maximum allowed.

The Concatenation Constraint

Counting Valid Code Words

How many 5-bit patterns satisfy our constraints? Let's enumerate:

5-bit patterns = 32 total

Invalid patterns (more than 1 leading zero):

00xxx: 8 patterns (but 01xxx are valid, so 00xxx = 8 invalid)

Invalid patterns (more than 2 trailing zeros):

xxx000: 4 patterns
But 00000 already counted above
Additional invalid: x1000, x0000 where x ≠ 0... (complex counting)

Direct count of valid patterns: Patterns with 0 leading zeros: 1xxxx (16 patterns) Patterns with 1 leading zero: 01xxx (8 patterns) Total first-constraint compliant: 24 patterns

From these, eliminate trailing-zero violations:

10000 (3 trailing zeros) ✗
01000 (3 trailing zeros) ✗
11000 (3 trailing zeros) ✗
etc.

Result: 23 valid code words

Of these:

16 are used for data (hex 0-F)
7 are available for control symbols
9 remaining 5-bit patterns are invalid

4B/5B Code Table - Data Symbols
Data (Hex)	Data (Binary)	4B/5B Code	of 1s	Notes
0	0000	11110	4	High transition density
1	0001	01001	2	Valid: 1 leading zero
2	0010	10100	2	Balanced
3	0011	10101	3	Balanced
4	0100	01010	2	Valid: 1 leading zero
5	0101	01011	3	Valid: 1 leading zero
6	0110	01110	3	Valid: 1 leading zero
7	0111	01111	4	Valid: 1 leading zero
8	1000	10010	2	Balanced
9	1001	10011	3	Balanced
A	1010	10110	3	Balanced
B	1011	10111	4	Balanced
C	1100	11010	3	Balanced
D	1101	11011	4	Balanced
E	1110	11100	3	2 trailing zeros (max)
F	1111	11101	4	Balanced

Control Symbols and Link Management

Control Symbol Definitions

4B/5B Control Symbols
Symbol	4B/5B Code	Function	Usage Context
I (Idle)	11111	Link Idle	Transmitted between frames to maintain synchronization
J (Start 1)	11000	Start of Frame (1st)	First symbol of preamble, used with K
K (Start 2)	10001	Start of Frame (2nd)	Second symbol of preamble, follows J
T (Terminate)	01101	End of Frame	Marks end of data in frame
R (Reserved)	00111	Reserved/Reset	Link reset or reserved for future use
S (Set)	11001	Reserved	Reserved for future use
H (Halt)	00100	Halt	Signals intentional halt (FDDI)

Frame Delimiting

The J-K Start Delimiter:

Frame transmission begins with the J-K symbol pair:

J = 11000 (violates normal code: would be invalid if not special)
K = 10001 (unique pattern)

The J-K combination:

Creates a unique bit pattern not found in data (11000 10001)
Signals unambiguous frame start
Provides additional synchronization reference
Cannot occur within valid data (J is not a data code)

The T Terminator:

Frames end with the T symbol (01101):

Signals end of data payload
Receiver knows to expect idle or new frame
Enables immediate turnaround in half-duplex

Idle Pattern and Link Maintenance

Continuous Idle Transmission:

Between frames, the transmitter continuously sends Idle symbols (11111):

Frame 1 [T] I I I I I I I I I I I [J K] Frame 2
                ↑
         Idle fill maintains clock lock

Why not just keep the line quiet?

Clock Maintenance: Receiver PLL needs transitions to stay locked
Link Status: Idle = link is up and functional
Activity Detection: Distinguishes active idle from cable disconnect
DC Balance: Idle pattern (11111) helps maintain DC equilibrium

Note on I Symbol: The Idle symbol (11111) has five 1s, seemingly violating our "no long runs" rule. However, when combined with MLT-3 encoding:

Each '1' causes a transition in MLT-3
11111 produces maximum transitions (excellent for clock recovery)
The concern was runs of zeros, not ones

Invalid Code Detection

Control Symbol Functions

•Frame Delimiting: J-K start delimiter and T terminator mark frame boundaries unambiguously
•Link Idle: I symbol transmitted between frames maintains clock synchronization
•Error Detection: Invalid codes (9 of 32 patterns) signal physical layer errors
•Special Actions: H, R, S symbols support link management functions
•Unambiguous Decoding: Control symbols cannot be confused with any data pattern

DC Balance, Running Disparity, and Spectral Properties

One limitation of 4B/5B is that it does not intrinsically guarantee DC balance. Understanding this limitation—and how systems work around it—reveals important principles of physical layer design.

The DC Balance Challenge

What is DC Balance?

A DC-balanced signal has equal energy in positive and negative excursions over time, resulting in a zero average voltage. DC balance is critical for:

Transformer Coupling: Transformers block DC; imbalanced signals cause baseline wander
AC-Coupled Links: Capacitors in the signal path block DC components
EMI Reduction: Balanced signals produce less electromagnetic interference

4B/5B's DC Imbalance:

Examine the code table:

Data	4B/5B Code	# of 1s	Disparity
0	11110	4	+4
1	01001	2	+2
...	...	...	...
F	11101	4	+4

Most codes have more 1s than 0s (disparity > 0). Random data will tend to produce more 1s than 0s, creating a DC offset.

How Systems Compensate

MLT-3 Encoding (Fast Ethernet):

4B/5B's DC imbalance is partially mitigated by MLT-3:

MLT-3 signal cycles: 0 → +V → 0 → -V → 0
Over time, positive and negative excursions tend to balance
The combination (4B/5B + MLT-3) is approximately DC-balanced for random data

Scrambling:

Fast Ethernet (100BASE-TX) adds a scrambler after 4B/5B encoding:

Polynomial: x¹¹ + x⁹ + 1
Randomizes the bit pattern
Distributes spectral energy
Improves DC balance for worst-case data patterns
Reduces pattern-dependent EMI

4b5b_dc_analysis.py
Python
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
class Encoder4B5B:
    """
    4B/5B Block Encoder with DC Balance Analysis
    
    Implements the standard 4B/5B encoding used in Fast Ethernet
    and FDDI, with analysis tools for understanding DC characteristics.
    """
    
    # Standard 4B/5B code table
    DATA_CODES = {
        0x0: 0b11110,  # 0000 -> 11110
        0x1: 0b01001,  # 0001 -> 01001
        0x2: 0b10100,  # 0010 -> 10100
        0x3: 0b10101,  # 0011 -> 10101
        0x4: 0b01010,  # 0100 -> 01010
        0x5: 0b01011,  # 0101 -> 01011
        0x6: 0b01110,  # 0110 -> 01110
        0x7: 0b01111,  # 0111 -> 01111
        0x8: 0b10010,  # 1000 -> 10010
        0x9: 0b10011,  # 1001 -> 10011
        0xA: 0b10110,  # 1010 -> 10110
        0xB: 0b10111,  # 1011 -> 10111
        0xC: 0b11010,  # 1100 -> 11010
        0xD: 0b11011,  # 1101 -> 11011
        0xE: 0b11100,  # 1110 -> 11100
        0xF: 0b11101,  # 1111 -> 11101
    }
    
    # Control symbols
    CONTROL_CODES = {
        'I': 0b11111,  # Idle
        'J': 0b11000,  # Start-of-frame 1
        'K': 0b10001,  # Start-of-frame 2
        'T': 0b01101,  # End-of-frame
        'R': 0b00111,  # Reset
        'S': 0b11001,  # Set (reserved)
        'H': 0b00100,  # Halt
    }
    
    # Invalid codes (can be used for error detection)
    INVALID_CODES = [
        0b00000, 0b00001, 0b00010, 0b00011,
        0b00101, 0b00110, 0b01000, 0b10000, 0b11111
    ]
    
    def encode_nibble(self, nibble: int) -> int:
        """Encode a 4-bit nibble to 5-bit code."""
        if nibble not in self.DATA_CODES:
            raise ValueError(f"Invalid nibble: {nibble}")
        return self.DATA_CODES[nibble]
    
    def encode_byte(self, byte: int) -> tuple[int, int]:
        """Encode a byte as two 5-bit codes (high nibble first)."""
        high = (byte >> 4) & 0xF
        low = byte & 0xF
        return (self.encode_nibble(high), self.encode_nibble(low))
    
    def encode_data(self, data: bytes) -> list[int]:
        """Encode byte array to list of 5-bit codes."""
        codes = []
        for byte in data:
            high, low = self.encode_byte(byte)
            codes.extend([high, low])
        return codes
    
    def calculate_disparity(self, code: int, bits: int = 5) -> int:
        """
        Calculate running disparity contribution.
        
        Disparity = (number of 1s) - (number of 0s)
        Positive disparity means more 1s than 0s.
        """
        ones = bin(code).count('1')
        zeros = bits - ones
        return ones - zeros
    
    def analyze_dc_balance(self, codes: list[int]) -> dict:
        """
        Analyze DC balance of encoded stream.
        
        Returns statistics on running disparity and DC offset tendency.
        """
        running_disparity = 0
        max_disparity = 0
        min_disparity = 0
        disparity_history = []
        
        for code in codes:
            disp = self.calculate_disparity(code)
            running_disparity += disp
            max_disparity = max(max_disparity, running_disparity)
            min_disparity = min(min_disparity, running_disparity)
            disparity_history.append(running_disparity)
        
        total_bits = len(codes) * 5
        avg_disparity = running_disparity / len(codes) if codes else 0
        
        return {
            "total_codes": len(codes),
            "total_bits": total_bits,
            "final_disparity": running_disparity,
            "max_disparity": max_disparity,
            "min_disparity": min_disparity,
            "avg_disparity_per_code": avg_disparity,
            "dc_offset_estimate": running_disparity / total_bits if total_bits else 0,
            "disparity_history": disparity_history
        }
    
    def check_run_length(self, codes: list[int]) -> dict:
        """
        Verify that encoded stream satisfies run-length constraints.
        
        4B/5B guarantees no more than 3 consecutive zeros.
        """
        # Convert to bit stream
        bits = []
        for code in codes:
            for i in range(4, -1, -1):
                bits.append((code >> i) & 1)
        
        max_zeros = 0
        current_zeros = 0
        
        for bit in bits:
            if bit == 0:
                current_zeros += 1
                max_zeros = max(max_zeros, current_zeros)
            else:
                current_zeros = 0
        
        return {
            "max_consecutive_zeros": max_zeros,
            "constraint_satisfied": max_zeros <= 3,
            "total_bits": len(bits)
        }
 
 
# Demonstration
if __name__ == "__main__":
    encoder = Encoder4B5B()
    
    # Encode sample data
    sample_data = bytes([0x00, 0xFF, 0xA5, 0x5A, 0x12, 0x34])
    print("4B/5B Encoding Analysis")
    print("=" * 60)
    print(f"Input data: {sample_data.hex().upper()}")
    
    codes = encoder.encode_data(sample_data)
    print(f"Encoded: {[format(c, '05b') for c in codes]}")
    
    # DC balance analysis
    dc_analysis = encoder.analyze_dc_balance(codes)
    print(f"\nDC Balance Analysis:")
    for key, value in dc_analysis.items():
        if key != "disparity_history":
            print(f"  {key}: {value}")
    
    # Run length check
    run_analysis = encoder.check_run_length(codes)
    print(f"\nRun Length Analysis:")
    for key, value in run_analysis.items():
        print(f"  {key}: {value}")

Comparison with DC-Balanced Codes

8B/10B (Gigabit Ethernet, Fibre Channel):

8B/10B provides guaranteed DC balance through running disparity control:

Property	4B/5B	8B/10B
Efficiency	80%	80%
DC Balance	Not guaranteed	Guaranteed
Max Run Length	3 zeros	5 identical
Control Symbols	7	12 K-codes
Complexity	Low	Medium
Used In	Fast Ethernet, FDDI	Gigabit Ethernet, FC

8B/10B Running Disparity:

Each 10-bit code comes in two versions: positive and negative disparity
Encoder alternates between versions to maintain running disparity near zero
Guarantees DC balance regardless of data pattern

4B/5B's lack of guaranteed DC balance is acceptable for Fast Ethernet because:

MLT-3 encoding provides inherent balance tendency
Scrambling randomizes patterns
Short cable runs (100m max) tolerate some baseline wander
Lower complexity reduces cost and power

The Complexity Trade-off

4B/5B in Fast Ethernet (100BASE-TX)

The Complete 100BASE-TX Signal Chain

Transmission Path:

[MII] → [4B/5B Encoder] → [Scrambler] → [NRZ-I] → [MLT-3] → [Line Driver] → Cable
  ↓           ↓              ↓           ↓          ↓
4-bit      5-bit         Randomized   Binary    3-level
nibbles    codes         stream       stream    analog

Rate Expansion:

MII (Media Independent Interface): 25 MHz × 4 bits = 100 Mbps
4B/5B output: 25 MHz × 5 bits = 125 Mbps = 125 Mbaud
MLT-3 fundamental: 125 Mbaud / 4 = 31.25 MHz

Stage-by-Stage Analysis

2. 4B/5B Encoding: Each 4-bit nibble is looked up in the code table, producing a 5-bit symbol. The encoder operates at 25 million nibbles/second, outputting 125 million bits/second.

3. Scrambling (NRZI Stream Cipher): The scrambler uses polynomial x¹¹ + x⁹ + 1:

scrambled_bit[n] = data_bit[n] XOR scrambled_bit[n-9] XOR scrambled_bit[n-11]

Scrambling provides:

Spectral whitening (spreads energy across frequencies)
Pattern randomization (breaks up repetitive data)
Improved DC balance (randomizes 1s and 0s)
EMI reduction (prevents discrete spectral lines)

4. NRZ-I Conversion: The scrambled stream is converted to NRZ-I (Non-Return to Zero Inverted):

'1' = transition (change state)
'0' = no transition (maintain state)

This intermediate step simplifies the MLT-3 implementation.

5. MLT-3 Encoding: The NRZ-I stream drives the MLT-3 state machine:

Transition: cycle through 0 → +V → 0 → -V → 0
No transition: maintain current level

6. Line Driving: The analog output driver delivers ±1V differential into the 100Ω cable impedance, with pre-emphasis to compensate for cable losses.

Converting Mermaid diagram...

Frame Structure with 4B/5B

Idle and Preamble:

...I I I I J K [SFD] [Dest MAC] [Src MAC] [Type/Len] [Data...] [FCS] T R...
           ↑   ↑
     Start  Preamble/SFD encoded as 4B/5B data symbols
     Delim

Inter-Packet Gap:

Minimum 96 bit times (960 ns at 100 Mbps)
Transmitted as Idle symbols (at least 12 Idles after T)
Allows receiver to process previous frame

Start of Frame:

J-K symbol pair (11000 10001)
Followed by preamble and SFD encoded as hex 55...5D
Receiver uses J-K to achieve precise symbol synchronization

End of Frame:

T symbol (01101) marks end of data
R symbols may follow for padding
Then continuous Idle until next frame

100BASE-TX Timing Specifications
Parameter	Value	Derivation
Data Rate	100 Mbps	User payload rate
4B/5B Symbol Rate	25 Msymbols/s	100 Mbps / 4 bits
Line Rate	125 Mbaud	25M × 5 bits
Symbol Period	8 ns	1 / 125M
Max Frequency (MLT-3)	31.25 MHz	125M / 4
Inter-Packet Gap	0.96 µs	96 bits at 100 Mbps
Max Cable Length	100 m	Signal integrity limit

Common Implementation Errors

4B/5B in FDDI and Beyond

FDDI: The Original 4B/5B Application

FDDI Overview:

Standard: ANSI X3T9.5, ISO 9314
Topology: Dual counter-rotating rings
Speed: 100 Mbps
Media: Multimode fiber (62.5/125 µm) or STP cable
Encoding: 4B/5B + NRZI (not MLT-3)

Why 4B/5B for FDDI?

FDDI required:

100 Mbps throughput: Matched contemporary mainframe I/O speeds
Long distances: Up to 2 km between nodes, 100 km total ring circumference
Reliable clocking: Token-ring timing is critical
Cost-effective PHY: Silicon of the 1980s had limited complexity

4B/5B delivered efficient encoding suitable for fiber optic transmission where DC balance was less critical (fiber uses intensity modulation).

FDDI Physical Layer Differences

FDDI vs 100BASE-TX:

Aspect	FDDI	100BASE-TX
Line Coding	NRZI	MLT-3
Media	Fiber / STP	UTP
Distance	2 km	100 m
Wavelength	1300 nm	N/A (electrical)
Topology	Ring	Star

NRZI in FDDI: FDDI uses NRZI (Non-Return to Zero Inverted) directly on fiber:

'1' = light transition (on→off or off→on)
'0' = no transition
4B/5B ensures enough transitions for clock recovery

Unlike electrical transmission, fiber doesn't have DC balance issues (you're modulating light intensity, not voltage). This simplified the FDDI design compared to 100BASE-TX's MLT-3 requirement.

FDDI Control Symbols

•Q (Quiet): 00000 - Line quiet (no signal)
•I (Idle): 11111 - Link idle, clock maintenance
•H (Halt): 00100 - Halt symbol for ring management
•J (Start 1): 11000 - First symbol of starting delimiter
•K (Start 2): 10001 - Second symbol of starting delimiter
•T (Terminate): 01101 - End of frame marker
•S (Set): 11001 - Reserved for SET operations

Other 4B/5B Applications

100BASE-FX (Fiber Fast Ethernet):

Uses 4B/5B + NRZI (like FDDI)
Multimode fiber, 1300 nm
2 km range (half-duplex), 412 m (full-duplex, timing constrained)
Popular in industrial and campus backbones

100VG-AnyLAN:

Competing standard to 100BASE-TX (lost the market)
Used 5B/6B encoding (different approach)
Demand-priority access instead of CSMA/CD

The Legacy of 4B/5B

4B/5B established principles that influenced all subsequent high-speed encoding:

Block Coding Concept: Map m-bit data to n-bit codes with guaranteed properties
Transition Density: Ensure enough edges for clock recovery
Control Symbols: Reserve codes for in-band signaling
Error Detection: Invalid codes indicate physical layer errors

These concepts evolved into:

8B/10B: Added DC balance (used in Gigabit Ethernet, Fibre Channel)
64B/66B: Higher efficiency for 10 Gigabit and beyond
128B/130B: Used in PCIe Gen 3+

Why FDDI Lost to Fast Ethernet

Summary: Mastering 4B/5B Encoding

Core Concepts to Remember

•Block Code Structure: 4-bit input nibbles map to 5-bit output codes via a fixed lookup table
•Run-Length Constraint: Maximum 3 consecutive zeros guaranteed (1 leading + 2 trailing zero limit)
•25% Overhead: Efficiency = 80% (5/4 expansion), much better than Manchester's 50%
•Control Symbols: J-K (start), T (terminate), I (idle) manage frame boundaries and link maintenance
•Error Detection: 9 invalid codes signal physical layer errors before CRC checking
•MLT-3 Synergy: Combined with MLT-3, enables 100 Mbps over Category 5 UTP at 31.25 MHz

4B/5B Quick Reference Card
Parameter	Value	Notes
Code Rate	4:5	4 data bits → 5 code bits
Efficiency	80%	Higher than Manchester (50%)
Max Run	3 zeros	Guaranteed by code design
Data Codes	16	Hex 0-F
Control Codes	7	I, J, K, T, R, S, H
Invalid Codes	9	Error detection capability
Primary Use	100BASE-TX, FDDI	Combined with MLT-3 or NRZI

4B/5B Advantages

•Simple lookup table implementation
•Guaranteed transition density
•Low overhead (only 25%)
•Built-in control symbols
•Physical layer error detection
•Proven in billions of devices

4B/5B Limitations

•No guaranteed DC balance
•Requires scrambling for EMI compliance
•Not self-clocking (needs additional encoding)
•Limited to moderate speeds
•Fixed code (no rate adaptation)
•Superseded by 8B/10B for higher speeds

Looking Ahead:

Page Complete

3 / 5