Computer NetworksDigital Transmission

Multilevel Coding

LevelIntermediate

Duration90 mins

TopicDigital Transmission

5 / 5

High-Speed Applications

Engineering the Impossible: Beyond 100 Gbps

The journey from 10 Mbps Ethernet in 1983 to 400 Gbps Ethernet today represents an astounding 40,000× increase in speed—achieved while dramatically reducing the cost per bit. This wasn't accomplished through brute force, but through the systematic application of multilevel coding principles you've studied throughout this module.

At terabit speeds, every technique matters: multilevel signaling (PAM-4, PAM-16) increases bits per symbol, advanced block codes (64B/66B, 256B/257B) maximize efficiency, forward error correction (FEC) enables operation at error rates that would be catastrophic without it, and sophisticated digital signal processing compensates for impairments that would make transmission impossible.

The Modern High-Speed Stack:

[Application Data]
        ↓
[MAC Layer: Framing, CRC]
        ↓
[PCS: Block Encoding (64B/66B, 256B/257B)]
        ↓
[FEC: Forward Error Correction]
        ↓
[PMA: PAM-4/PAM-16 Modulation]
        ↓
[PMD: SerDes, Equalization, CDR]
        ↓
[Physical Medium: Fiber, Cu, Backplane]

This page synthesizes everything you've learned about multilevel coding and applies it to understanding how real-world 100G, 400G, and 800G systems operate.

What You Will Master

By completing this page, you will understand how PAM-4 modulation enables doubling of data rates, how 64B/66B and 256B/257B encodings achieve near-theoretical efficiency, why FEC became mandatory at high speeds, the architecture of modern 100G/400G transceivers, and the engineering trade-offs that determine system design. This knowledge positions you to understand the physical layer of any current or future high-speed networking standard.

PAM-4: Doubling Throughput at the Physical Layer

PAM-4 (Pulse Amplitude Modulation - 4 levels) represents the logical evolution of 2B1Q concepts to high-speed networking. By encoding 2 bits per symbol, PAM-4 doubles the data rate for a given baud rate—or equivalently, halves the required bandwidth for a given data rate.

PAM-4 Fundamentals

Voltage Levels:

Dibit	PAM-4 Level	Typical Voltage
00	-3 (L0)	-150 mV
01	-1 (L1)	-50 mV
11	+1 (L2)	+50 mV
10	+3 (L3)	+150 mV

Note: The mapping uses Gray code (adjacent levels differ by one bit) to minimize bit errors from amplitude noise.

The NRZ-to-PAM-4 Transition

Why PAM-4 became necessary:

At 25 Gbps per lane (NRZ), the fundamental frequency is 12.5 GHz. Pushing to 50 Gbps per lane with NRZ would require 25 GHz—problematic for:

Copper cables (high attenuation at 25 GHz)
Legacy connectors (impedance discontinuities)
PCB traces (skin effect losses)
IC I/O (power consumption)

PAM-4 Solution:

50 Gbps data rate with PAM-4:

Baud rate: 25 Gbaud (same as 25 Gbps NRZ)
Requires 2 bits per symbol
Same bandwidth, double the throughput
Enables 50G/lane → 400G with 8 lanes

NRZ vs PAM-4 Comparison
Parameter	NRZ (2-level)	PAM-4 (4-level)	Impact
Bits/Symbol	1	2	2× throughput
Voltage Levels	2	4	3× smaller eye
SNR Requirement	~15 dB	~21 dB	6 dB penalty
Error Rate (raw)	1e-12	1e-4 to 1e-6	FEC required
50G Lane Rate	50 GBaud	25 GBaud	Half bandwidth
Equalization	Moderate	Aggressive	More DSP power

The PAM-4 SNR Penalty

PAM-4's 3 decision thresholds (between 4 levels) are 3× closer together than NRZ's single threshold. This makes PAM-4 approximately 9.5 dB more sensitive to noise. The additional 6+ dB SNR requirement means PAM-4 systems operate at much higher raw error rates and absolutely require FEC to achieve acceptable bit error rates.

PAM-4 in Ethernet Standards

802.3bs (2017) - 200G/400G Ethernet:

200GBASE-DR4: 4 lanes × 50G PAM-4 = 200 Gbps
400GBASE-FR8: 8 lanes × 50G PAM-4 = 400 Gbps
400GBASE-DR4: 4 lanes × 100G PAM-4 = 400 Gbps

802.3ck (2022) - 100G/Lane:

100GBASE-CR1: 1 lane × 100G PAM-4 = 100 Gbps over copper
400GBASE-CR4: 4 lanes × 100G PAM-4 = 400 Gbps
800GBASE-CR8: 8 lanes × 100G PAM-4 = 800 Gbps

Lane Rate Evolution:

Gen 1: 10G NRZ (10 Gbaud)     → 10/40/100GbE
Gen 2: 25G NRZ (25 Gbaud)     → 25/100GbE  
Gen 3: 50G PAM-4 (26.5625 Gbaud) → 50/200/400GbE
Gen 4: 100G PAM-4 (53.125 Gbaud) → 100/400/800GbE
Gen 5: 200G PAM-4 (106.25 Gbaud) → 800G/1.6TbE (emerging)

Eye Diagram Characteristics

The PAM-4 eye diagram shows three "eyes" stacked vertically:

       ╱╲╱╲
      ╱  ╲ ╲     ← Upper eye (L3/L2 transitions)
     ╱    ╲ ╲
    │      │ │
     ╲    ╱ ╱
      ╲  ╱ ╱     ← Middle eye (L2/L1 transitions)
       ╲╱╲╱
      ╱  ╲ ╲
     ╱    ╲ ╲    ← Lower eye (L1/L0 transitions)
    │      │ │
     ╲    ╱ ╱
      ╲  ╱ ╱
       ╲╱╲╱

Critical Metrics:

Eye Height: Vertical opening (noise margin)
Eye Width: Horizontal opening (timing margin)
Linearity: Symmetry between eyes (amplitude distortion sensitivity)

PAM-4 Implementation Challenges

•Reduced Noise Margins: 3× smaller eye height requires superior signal integrity and noise control
•Mandatory FEC: Raw error rates of 1e-4 require powerful forward error correction to achieve 1e-15 BER
•Linearity Requirements: DACs and drivers must maintain accurate voltage ratios across all levels
•Crosstalk Sensitivity: Multi-level signaling amplifies near-end and far-end crosstalk effects
•CDR Complexity: Clock recovery from 4-level signals requires more sophisticated algorithms
•Power Consumption: Additional DSP for equalization and FEC increases transceiver power significantly

64B/66B and Beyond: Maximizing Efficiency

As speeds increased beyond 8B/10B's practical limits, the networking industry developed new block coding schemes that maximize efficiency while maintaining essential properties like clock recovery and frame delimiting.

64B/66B Encoding

Invented for 10 Gigabit Ethernet (802.3ae, 2002)

64B/66B achieves 96.97% efficiency (vs 8B/10B's 80%) by using a 2-bit sync header instead of per-byte encoding:

Block Structure:

┌──────────┬──────────────────────────────────────────────────────────┐
│ Sync (2) │              Payload (64 bits)                          │
├──────────┼──────────────────────────────────────────────────────────┤
│    01    │ D0 D1 D2 D3 D4 D5 D6 D7  (all 8 bytes are data)        │
│    10    │ Type + Control/Data mix  (contains at least 1 control)  │
└──────────┴──────────────────────────────────────────────────────────┘

Sync Header Properties:

Header	Meaning	Transition Guaranteed
01	Data block	Yes (bit 0≠1)
10	Control block	Yes (bit 0≠1)
00, 11	Invalid	Error if received

The 01 or 10 header guarantees a bit transition every 66 bits—sufficient for clock recovery when combined with scrambling.

Scrambling:

The 64-bit payload is scrambled with polynomial x⁵⁸ + x³⁹ + 1:

Provides DC balance (statistical, not deterministic)
Prevents long runs of identical bits
Spreads spectral energy (reduces EMI peaks)
Self-synchronizing after ~58 bits

64b66b_encoder.py
Python
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class Encoder64B66B:
    """
    64B/66B Encoder with Scrambling
    
    Demonstrates the encoding used in 10G+ Ethernet.
    The payload is scrambled for DC balance; the sync header
    provides block alignment.
    """
    
    SYNC_DATA = 0b01      # Data block sync header
    SYNC_CONTROL = 0b10   # Control block sync header
    
    # Control block type encoding (8 bits following sync)
    BLOCK_TYPES = {
        'idle':    0x00,  # All idles
        'start':   0x33,  # Start of frame  
        'term_0':  0x87,  # Terminate at byte 0
        'term_7':  0xFF,  # Terminate at byte 7
        'error':   0x1E,  # Error propagation
        'ordered': 0x4B,  # Ordered set
    }
    
    def __init__(self):
        # Scrambler state (58-bit LFSR)
        self.lfsr = 0x3FFFFFFFFFFFFFF  # Non-zero initial state
        self.scrambler_poly = (58, 39)  # x^58 + x^39 + 1
    
    def scramble_bit(self, bit: int) -> int:
        """
        Self-synchronizing scrambler: out = in XOR lfsr[58] XOR lfsr[39]
        """
        feedback = ((self.lfsr >> 57) ^ (self.lfsr >> 38)) & 1
        out = bit ^ feedback
        # Shift LFSR with input bit
        self.lfsr = ((self.lfsr << 1) | bit) & 0x3FFFFFFFFFFFFFF
        return out
    
    def scramble_block(self, payload: int) -> int:
        """Scramble 64-bit payload."""
        scrambled = 0
        for i in range(63, -1, -1):
            bit = (payload >> i) & 1
            scrambled_bit = self.scramble_bit(bit)
            scrambled = (scrambled << 1) | scrambled_bit
        return scrambled
    
    def encode_data_block(self, data: bytes) -> int:
        """
        Encode 8 bytes of data to 66-bit block.
        
        Returns:
            66-bit value: 2-bit sync + 64-bit scrambled payload
        """
        if len(data) != 8:
            raise ValueError("Data block must be exactly 8 bytes")
        
        # Pack bytes into 64-bit payload (big-endian)
        payload = int.from_bytes(data, 'big')
        
        # Scramble payload
        scrambled = self.scramble_block(payload)
        
        # Prepend sync header
        block = (self.SYNC_DATA << 64) | scrambled
        
        return block
    
    def encode_control_block(self, block_type: str, control_data: int = 0) -> int:
        """
        Encode a control block (contains at least one control character).
        
        Args:
            block_type: Type of control block ('idle', 'start', etc.)
            control_data: Additional control/data bytes (56 bits)
        
        Returns:
            66-bit value: 2-bit sync + 8-bit type + 56-bit control/data
        """
        type_field = self.BLOCK_TYPES.get(block_type, 0x00)
        payload = (type_field << 56) | (control_data & 0x00FFFFFFFFFFFFFF)
        
        # Scramble payload
        scrambled = self.scramble_block(payload)
        
        # Prepend sync header
        block = (self.SYNC_CONTROL << 64) | scrambled
        
        return block
    
    def format_block(self, block: int) -> str:
        """Format 66-bit block for display."""
        sync = (block >> 64) & 0x3
        payload = block & 0xFFFFFFFFFFFFFFFF
        return f"[{sync:02b}] {payload:016X}"
 
 
# Demonstration
if __name__ == "__main__":
    encoder = Encoder64B66B()
    
    print("64B/66B Encoding Demonstration")
    print("=" * 60)
    
    # Encode data block
    data = bytes([0x55, 0xAA, 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC])
    block = encoder.encode_data_block(data)
    print(f"Data: {data.hex().upper()}")
    print(f"Block: {encoder.format_block(block)}")
    
    # Encode idle block
    idle_block = encoder.encode_control_block('idle')
    print(f"\nIdle block: {encoder.format_block(idle_block)}")
    
    # Encode start block
    start_block = encoder.encode_control_block('start')
    print(f"Start block: {encoder.format_block(start_block)}")

256B/257B and 512B/513B Encoding

Extreme Efficiency for 100G+ Lanes:

As lane rates increased to 100G+, even 64B/66B's 3% overhead became significant. Newer standards use larger block sizes:

Encoding	Efficiency	Overhead	Primary Use
8B/10B	80.00%	25.00%	1G/10G legacy
64B/66B	96.97%	3.03%	10G/25G/40G
256B/257B	99.61%	0.39%	100G/400G*
512B/513B	99.80%	0.20%	Emerging

*Often used in conjunction with additional FEC framing.

256B/257B Structure:

Similar to 64B/66B, but with 4× larger blocks:

1-bit sync header
256-bit payload
Payload contains four 64B/66B-style blocks (transcoded)

RS-FEC Interaction:

At 100G+ speeds, Reed-Solomon FEC is applied after encoding:

RS(544,514) for 100G/400G
Adds FEC overhead (~6%)
Combined efficiency: 256B/257B × RS ≈ 93.5%

Why Block Size Matters

Larger Blocks = Higher Efficiency:

Overhead = sync_bits / block_bits

64B/66B:  2/66 = 3.03%
256B/257B: 1/257 = 0.39%
512B/513B: 1/513 = 0.20%

Larger Blocks = Higher Latency:

Block encoding introduces alignment latency:

64B/66B at 25G: 2.64 ns per block
256B/257B at 100G: 2.57 ns per block

For latency-sensitive applications (HPC, trading), this becomes significant.

The Encoding-FEC Interaction

Modern high-speed standards don't apply encoding in isolation—they're designed as integrated systems. 256B/257B encoding is often paired with specific FEC codes, and the block boundaries are aligned. This co-design optimizes both efficiency and error correction performance.

Forward Error Correction: Enabling Imperfect Transmission

At speeds beyond 25 Gbps, forward error correction (FEC) transitions from optional enhancement to absolute necessity. PAM-4 modulation operates at raw bit error rates (10⁻⁴ to 10⁻⁶) that would be catastrophic for applications without FEC.

Why FEC Became Mandatory

The SNR Budget Crisis:

As speeds increase, the available signal-to-noise ratio decreases:

Higher frequencies = more cable/connector loss
PAM-4 = 9.5 dB penalty vs NRZ
Smaller features = more device noise
Higher density = more crosstalk

Result: 100G PAM-4 systems operate with raw BER of ~10⁻⁴ (1 error per 10,000 bits). Without FEC, a 100 Gbps link would see 10 million errors per second!

Reed-Solomon FEC in Ethernet

RS(544,514) - The Workhorse Code:

IEEE 802.3 specifies Reed-Solomon FEC for high-speed Ethernet:

Parameter	Value	Meaning
n (codeword length)	544 symbols	Total symbols per block
k (data symbols)	514 symbols	User data capacity
t (correction capability)	15 symbols	Max correctable errors
Symbol size	10 bits	Each symbol is 10 bits
Overhead	5.8%	(544-514)/514
Coding gain	~6 dB	Equivalent SNR improvement

How It Works:

Interleaving: Data is spread across multiple FEC codewords to disperse burst errors
Encoding: Parity symbols calculated using Galois field arithmetic
Transmission: Data + parity sent over the channel
Syndrome Calculation: Receiver computes error indicators
Error Correction: Up to 15 symbol errors per codeword corrected
Deinterleaving: Original data order restored

FEC Performance: Raw BER to Post-FEC BER
Raw BER (Input)	Post-FEC BER	Reduction Factor	Viable?
1e-3	~1e-6	1,000×	Marginal
1e-4	~1e-12	10⁸×	≈Good
1e-5	~1e-15	10¹⁰×	Excellent
1e-6	<1e-18	10¹²×	Exceeds measurement

The FEC Cliff

FEC codes exhibit a 'cliff' behavior: if the input BER is below a threshold (called the 'FEC limit'), the output BER drops to effectively zero. If above the threshold, the output BER degrades rapidly. This creates a sharp transition between 'working' and 'not working'—helpful for link qualification but unforgiving of marginal links.

FEC Types in High-Speed Networking

KR-FEC (Firecode):

Simple FEC for 10GBASE-KR, 40GBASE-KR4
RS(2112, 2080) - weak correction capability
Corrects 1 symbol error per 2112 symbols
Low latency (~100 ns)
Adequate for NRZ signaling

KP-FEC (RS-FEC):

Stronger FEC for 25G+ PAM-4
RS(544, 514) over GF(2¹⁰)
Corrects up to 15 symbol errors per codeword
Higher latency (~70-100 ns)
Mandatory for PAM-4 operation

CFEC (Concatenated FEC):

Even stronger FEC for long-reach optics
Inner code (RS) + Outer code (BCH or LDPC)
Corrects raw BER up to ~10⁻²
Higher latency (~400+ ns)
Used in coherent optics (400ZR, etc.)

FEC and Latency

FEC Latency Components:

Stage	Latency	Notes
Encoding	~10 ns	Parity calculation
Serializing	~20 ns	Block assembly
Deserializing	~20 ns	Symbol extraction
Syndrome	~15 ns	Error detection
Correction	~30 ns	Error location & fix
Total	~100 ns	Adds to link latency

For ultra-low-latency applications (HFT, HPC):

Some links operate in 'FEC bypass' mode
Higher BER tolerance required
Limited to short, high-quality channels

FEC Deployment Considerations

•PAM-4 Requirement: RS-FEC is mandatory for all PAM-4 links; NRZ may operate without FEC on short reaches
•Latency Trade-off: Stronger FEC codes introduce more latency; choose based on application needs
•Power Consumption: FEC encoders/decoders consume significant power in high-speed SerDes; ~1-2W typical
•Interoperability: FEC type and parameters must match at both ends; IEEE 802.3 specifies exactly
•Monitoring: FEC corrected/uncorrected error counts are key health metrics for link monitoring
•Margin Estimation: Pre-FEC BER indicates actual channel quality; post-FEC BER shows user experience

Modern Transceiver Architecture

Modern high-speed transceivers are marvels of integration, combining all the multilevel coding, modulation, and signal processing techniques into compact modules. Understanding their architecture reveals how theory becomes practice.

Pluggable Transceiver Evolution

Pluggable Transceiver Form Factor Evolution
Form Factor	Speed	Power	Encoding Era
SFP	1-10G	1W	8B/10B
SFP+	10G	1.5W	64B/66B
SFP28	25G	2W	64B/66B + KR-FEC
QSFP+	40G	3.5W	64B/66B (4×10G)
QSFP28	100G	4.5W	256B/257B + RS-FEC
QSFP56	200G	7W	PAM-4 + RS-FEC
QSFP-DD	400G	14W	PAM-4 + RS-FEC
OSFP	400-800G	20W	PAM-4 + CFEC

Internal Architecture: 400G QSFP-DD

Block Diagram:

┌─────────────────────────────────────────────────────────────────┐
│                        QSFP-DD 400G Module                     │
├─────────────────────────────────────────────────────────────────┤
│                                                                 │
│  ┌───────┐   ┌─────────┐   ┌─────────┐   ┌─────────┐   ┌─────┐│
│  │ Cage  │   │ Host    │   │ Retimer/│   │ Laser   │   │Fiber││
│  │ I/F   │◄─►│ SerDes  │◄─►│ DSP     │◄─►│ Driver  │◄─►│ I/F ││
│  │8×100G │   │ (CTLE   │   │ (FEC,   │   │ (EML or │   │ MPO ││
│  │PAM-4  │   │  DFE)   │   │ gearbox)│   │ VCSEL)  │   │ 8ch ││
│  └───────┘   └─────────┘   └─────────┘   └─────────┘   └─────┘│
│                                                                 │
│  ┌────────────────────────────────────────────────────────────┐│
│  │                  Power & Thermal Management                 ││
│  │   14W TDP | 70°C max case temp | Active cooling support   ││
│  └────────────────────────────────────────────────────────────┘│
└─────────────────────────────────────────────────────────────────┘

Component Functions:

1. Host SerDes (on switch ASIC):

Receives 8×100G PAM-4 electrical signals from module
Performs CTLE (Continuous Time Linear Equalizer)
DFE (Decision Feedback Equalizer)
CDR (Clock and Data Recovery)

2. Retimer/DSP (in module):

Regenerates signal for long module traces
FEC encoding/decoding
Gearbox: translates host lanes to optical lanes (e.g., 8×100G → 4×100G)
PAM-4 to NRZ conversion if needed for optics

3. Laser Driver:

EML (Electro-absorption Modulated Laser) for long reach
DML (Directly Modulated Laser) for short reach
VCSEL (Vertical Cavity Surface Emitting Laser) for MMF

4. Fiber Interface:

MPO-12 or MPO-16 connector for parallel optics
LC duplex for single-lane coherent optics

Converting Mermaid diagram...

DSP Power and Complexity

The DSP Dilemma:

Modern transceivers contain sophisticated DSPs that consume significant power:

Function	Power (approx)	Why Needed
ADC (8× 100G)	2W	PAM-4 symbol detection
Equalization	3W	Channel compensation
FEC Decode	2W	Error correction
Clock Recovery	1W	Timing extraction
FEC Encode	1W	Parity generation
DAC (8× 100G)	2W	PAM-4 generation
Control/Other	3W	Management, thermal
Total	~14W	Module TDP

The Industry Response:

Linear Drive Optics: Eliminate DSP by using higher-quality lasers and shorter reaches
Co-packaged Optics: Integrate optics directly on switch ASIC, eliminating module DSP
Advanced Process Nodes: 7nm and 5nm DSPs reduce power significantly
LPO (Low Power Optics): Simplified modules for short data center reaches

The Gearbox Concept

A 'gearbox' converts between different lane configurations. For example, a 400G module might receive 8×50G from the host but transmit 4×100G optically. The gearbox performs this lane rate and count conversion. Understanding gearboxes is essential for matching host interfaces to optical standards.

Emerging Technologies: Beyond 800 Gbps

The networking industry is already developing technologies for 1.6 Tbps Ethernet and beyond. These next-generation systems push multilevel coding to new extremes while introducing revolutionary new techniques.

800G and 1.6T Ethernet

IEEE 802.3df (2024+) - 800G/1.6T Ethernet:

Speed	Lane Configuration	Encoding	Status
800G	8×100G PAM-4	256B/257B + RS	Ratified
800G	4×200G PAM-4	256B/257B + RS	In development
1.6T	8×200G PAM-4	TBD	Study group
1.6T	16×100G PAM-4	256B/257B + RS	Proposed

Key Challenges for 200G/Lane:

106.25 GBaud symbol rate
Channel bandwidth requirements exceed current copper/PCB limits
Requires either:
- Higher modulation (PAM-6/PAM-8)
- Advanced FEC with higher coding gain
- Shorter reaches
- New materials (low-loss laminates)

PAM-6 and PAM-8 Modulation

Beyond PAM-4:

Modulation	Levels	Bits/Symbol	SNR Penalty vs PAM-4
PAM-4	4	2	Reference
PAM-6	6	2.58	+4 dB
PAM-8	8	3	+7 dB
PAM-16	16	4	+14 dB

Current Research:

PAM-6/PAM-8 for electrical backplanes
Enables higher throughput without increased bandwidth
Requires even more powerful FEC (LDPC, Turbo codes)
DSP complexity and power increase significantly

Coherent Optics in Data Centers

The Coherent Revolution:

Coherent detection, long used in telecom, is entering the data center:

Coherent vs Direct Detect:

Property	Direct Detect	Coherent
Detection	Intensity	Phase & amplitude
Modulation	PAM	QAM (16-QAM, 64-QAM)
Dimensions	1 (intensity)	4 (I, Q, polarization)
Spectral efficiency	~1 bit/Hz	4-8 bits/Hz
DSP complexity	Moderate	Very high
Reach	<10 km	100+ km

400ZR and 400ZR+:

Coherent optics in QSFP-DD/OSFP form factor
400 Gbps over 80+ km single-mode fiber
16-QAM modulation on two polarizations
CFEC with soft-decision decoding

Data Center Interconnect (DCI):

Connects data centers 10-100 km apart
Coherent optics avoid regeneration
Single fiber pair carries 400 Gbps
Future: 800 Gbps, 1.2 Tbps coherent pluggables

Co-Packaged Optics (CPO)

The Final Integration Frontier:

CPO integrates optical engines directly on the switch ASIC package:

┌─────────────────────────────────────────────┐
│               Switch Package                │
│  ┌─────────────────────────────────────┐   │
│  │           Switch ASIC               │   │
│  │      (51.2 Tbps switching)          │   │
│  └──────────────┬──────────────────────┘   │
│                 │ Very short traces        │
│  ┌──────────────┴──────────────────────┐   │
│  │      Co-Packaged Optical Engine     │   │
│  │  (32× 400G = 12.8 Tbps I/O)         │   │
│  └─────────────────────────────────────┘   │
│                 │ Fiber ribbon             │
└─────────────────┼─────────────────────────┘
                  ↓
              Fiber plant

Advantages:

Eliminates module-to-ASIC traces (major power savings)
Reduces latency (no retimer needed)
Enables higher bandwidth density
Lower cost per Gbps at scale

Challenges:

Reliability (no hot-swap at CPO level)
Thermal management (optics on hot ASIC)
Ecosystem development (new manufacturing)

Future Directions

•Higher Modulation: PAM-6, PAM-8 for electrical; 64-QAM, 256-QAM for coherent optics
•Stronger FEC: LDPC and Turbo codes with soft-decision decoding approaching Shannon limit
•Co-Packaged Optics: Integration of optics on switch ASICs for >25 Tbps switch capacity
•Silicon Photonics: CMOS-compatible optical components for cost reduction
•Machine Learning: ML-based equalization and CDR for complex channels
•Photonic Computing: Optical domain processing to reduce electrical DSP power

The Shannon Limit

Shannon's theorem defines the maximum data rate for any channel. Modern coherent systems with soft-decision FEC operate within ~1-2 dB of this theoretical limit. Further speed increases must come from more bandwidth (wavelengths) or more dimensions (spatial modes), not coding efficiency—we're approaching the fundamental limits of physics.

Summary: Multilevel Coding in Modern Networks

This module has taken you on a journey from the fundamental principles of multilevel coding to the cutting edge of terabit networking. The techniques you've studied—MLT-3, 2B1Q, 4B/5B, 8B/10B, and their modern successors—form the foundation of every high-speed network link in operation today.

Let's consolidate the essential knowledge from this comprehensive module:

Core Concepts to Remember

•Multilevel Signaling Principle: Using L voltage levels encodes log₂(L) bits per symbol, trading noise margin for bandwidth efficiency
•Block Coding Trade-offs: mB/nB codes add redundancy (n>m) to guarantee clock recovery, DC balance, and error detection
•PAM-4 Revolution: Doubles throughput per baud but requires FEC due to 9.5 dB SNR penalty vs NRZ
•FEC Necessity: Modern links operate at raw BER ~10⁻⁴; RS-FEC (~10⁻¹² post-FEC) is mandatory beyond 25 Gbps
•Efficiency Evolution: 8B/10B (80%) → 64B/66B (97%) → 256B/257B (99.6%) enables higher net throughput
•System Integration: Modern transceivers combine modulation, encoding, FEC, and DSP into integrated signal chains

Module Quick Reference: Encoding Schemes
Scheme	Efficiency	DC Balance	Primary Era
MLT-3	80% (w/4B5B)	Good	100M (1995)
2B1Q	100%*	Scrambled	ISDN/DSL (1988)
4B/5B	80%	Poor	100M/FDDI (1990)
8B/10B	80%	Guaranteed	1G/FC (1998)
64B/66B	97%	Scrambled	10G/25G (2002)
256B/257B	99.6%	Scrambled	100G+ (2017)
PAM-4 (signaling)	2 bits/sym	N/A	50G+ (2017)

*2B1Q efficiency is 100% for the line code itself; overhead comes from framing.

The Engineering Mindset:

Throughout this module, you've seen that every encoding decision involves trade-offs:

Bandwidth efficiency vs. noise immunity
DC balance vs. implementation complexity
Error detection vs. overhead
Latency vs. error correction strength

There is no universally "best" encoding—only the best choice for specific speed, distance, cost, and reliability requirements. Understanding these trade-offs is what separates networking specialists from generalists.

What You Now Understand

•Why MLT-3 enabled Fast Ethernet over Cat 5
•How 2B1Q doubled ISDN efficiency
•Why 4B/5B + MLT-3 is a perfect pair
•How 8B/10B guarantees DC balance
•Why PAM-4 + FEC is essential for 100G+
•How modern transceivers integrate everything

Skills You Can Apply

•Evaluate encoding schemes for new designs
•Interpret eye diagrams and signal quality
•Understand FEC metrics and limits
•Troubleshoot physical layer issues
•Specify transceiver requirements
•Anticipate future technology evolution

Module Complete: Multilevel Coding Mastered

Congratulations! You have completed the Multilevel Coding module. You now possess comprehensive knowledge of how line coding techniques evolved from simple MLT-3 to sophisticated PAM-4 + FEC systems. This understanding of the physical layer is essential for anyone working with high-speed networks, from data center engineers to system architects to networking researchers.

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Computer NetworksDigital Transmission

Multilevel Coding

LevelIntermediate

Duration90 mins

TopicDigital Transmission

5 / 5

High-Speed Applications

Engineering the Impossible: Beyond 100 Gbps

The Modern High-Speed Stack:

[Application Data]
        ↓
[MAC Layer: Framing, CRC]
        ↓
[PCS: Block Encoding (64B/66B, 256B/257B)]
        ↓
[FEC: Forward Error Correction]
        ↓
[PMA: PAM-4/PAM-16 Modulation]
        ↓
[PMD: SerDes, Equalization, CDR]
        ↓
[Physical Medium: Fiber, Cu, Backplane]

This page synthesizes everything you've learned about multilevel coding and applies it to understanding how real-world 100G, 400G, and 800G systems operate.

What You Will Master

PAM-4: Doubling Throughput at the Physical Layer

PAM-4 Fundamentals

Voltage Levels:

Dibit	PAM-4 Level	Typical Voltage
00	-3 (L0)	-150 mV
01	-1 (L1)	-50 mV
11	+1 (L2)	+50 mV
10	+3 (L3)	+150 mV

Note: The mapping uses Gray code (adjacent levels differ by one bit) to minimize bit errors from amplitude noise.

The NRZ-to-PAM-4 Transition

Why PAM-4 became necessary:

At 25 Gbps per lane (NRZ), the fundamental frequency is 12.5 GHz. Pushing to 50 Gbps per lane with NRZ would require 25 GHz—problematic for:

Copper cables (high attenuation at 25 GHz)
Legacy connectors (impedance discontinuities)
PCB traces (skin effect losses)
IC I/O (power consumption)

PAM-4 Solution:

50 Gbps data rate with PAM-4:

Baud rate: 25 Gbaud (same as 25 Gbps NRZ)
Requires 2 bits per symbol
Same bandwidth, double the throughput
Enables 50G/lane → 400G with 8 lanes

NRZ vs PAM-4 Comparison
Parameter	NRZ (2-level)	PAM-4 (4-level)	Impact
Bits/Symbol	1	2	2× throughput
Voltage Levels	2	4	3× smaller eye
SNR Requirement	~15 dB	~21 dB	6 dB penalty
Error Rate (raw)	1e-12	1e-4 to 1e-6	FEC required
50G Lane Rate	50 GBaud	25 GBaud	Half bandwidth
Equalization	Moderate	Aggressive	More DSP power

The PAM-4 SNR Penalty

PAM-4 in Ethernet Standards

802.3bs (2017) - 200G/400G Ethernet:

200GBASE-DR4: 4 lanes × 50G PAM-4 = 200 Gbps
400GBASE-FR8: 8 lanes × 50G PAM-4 = 400 Gbps
400GBASE-DR4: 4 lanes × 100G PAM-4 = 400 Gbps

802.3ck (2022) - 100G/Lane:

100GBASE-CR1: 1 lane × 100G PAM-4 = 100 Gbps over copper
400GBASE-CR4: 4 lanes × 100G PAM-4 = 400 Gbps
800GBASE-CR8: 8 lanes × 100G PAM-4 = 800 Gbps

Lane Rate Evolution:

Gen 1: 10G NRZ (10 Gbaud)     → 10/40/100GbE
Gen 2: 25G NRZ (25 Gbaud)     → 25/100GbE  
Gen 3: 50G PAM-4 (26.5625 Gbaud) → 50/200/400GbE
Gen 4: 100G PAM-4 (53.125 Gbaud) → 100/400/800GbE
Gen 5: 200G PAM-4 (106.25 Gbaud) → 800G/1.6TbE (emerging)

Eye Diagram Characteristics

The PAM-4 eye diagram shows three "eyes" stacked vertically:

       ╱╲╱╲
      ╱  ╲ ╲     ← Upper eye (L3/L2 transitions)
     ╱    ╲ ╲
    │      │ │
     ╲    ╱ ╱
      ╲  ╱ ╱     ← Middle eye (L2/L1 transitions)
       ╲╱╲╱
      ╱  ╲ ╲
     ╱    ╲ ╲    ← Lower eye (L1/L0 transitions)
    │      │ │
     ╲    ╱ ╱
      ╲  ╱ ╱
       ╲╱╲╱

Critical Metrics:

Eye Height: Vertical opening (noise margin)
Eye Width: Horizontal opening (timing margin)
Linearity: Symmetry between eyes (amplitude distortion sensitivity)

PAM-4 Implementation Challenges

•Reduced Noise Margins: 3× smaller eye height requires superior signal integrity and noise control
•Mandatory FEC: Raw error rates of 1e-4 require powerful forward error correction to achieve 1e-15 BER
•Linearity Requirements: DACs and drivers must maintain accurate voltage ratios across all levels
•Crosstalk Sensitivity: Multi-level signaling amplifies near-end and far-end crosstalk effects
•CDR Complexity: Clock recovery from 4-level signals requires more sophisticated algorithms
•Power Consumption: Additional DSP for equalization and FEC increases transceiver power significantly

64B/66B and Beyond: Maximizing Efficiency

64B/66B Encoding

Invented for 10 Gigabit Ethernet (802.3ae, 2002)

64B/66B achieves 96.97% efficiency (vs 8B/10B's 80%) by using a 2-bit sync header instead of per-byte encoding:

Block Structure:

┌──────────┬──────────────────────────────────────────────────────────┐
│ Sync (2) │              Payload (64 bits)                          │
├──────────┼──────────────────────────────────────────────────────────┤
│    01    │ D0 D1 D2 D3 D4 D5 D6 D7  (all 8 bytes are data)        │
│    10    │ Type + Control/Data mix  (contains at least 1 control)  │
└──────────┴──────────────────────────────────────────────────────────┘

Sync Header Properties:

Header	Meaning	Transition Guaranteed
01	Data block	Yes (bit 0≠1)
10	Control block	Yes (bit 0≠1)
00, 11	Invalid	Error if received

The 01 or 10 header guarantees a bit transition every 66 bits—sufficient for clock recovery when combined with scrambling.

Scrambling:

The 64-bit payload is scrambled with polynomial x⁵⁸ + x³⁹ + 1:

Provides DC balance (statistical, not deterministic)
Prevents long runs of identical bits
Spreads spectral energy (reduces EMI peaks)
Self-synchronizing after ~58 bits

64b66b_encoder.py
Python
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class Encoder64B66B:
    """
    64B/66B Encoder with Scrambling
    
    Demonstrates the encoding used in 10G+ Ethernet.
    The payload is scrambled for DC balance; the sync header
    provides block alignment.
    """
    
    SYNC_DATA = 0b01      # Data block sync header
    SYNC_CONTROL = 0b10   # Control block sync header
    
    # Control block type encoding (8 bits following sync)
    BLOCK_TYPES = {
        'idle':    0x00,  # All idles
        'start':   0x33,  # Start of frame  
        'term_0':  0x87,  # Terminate at byte 0
        'term_7':  0xFF,  # Terminate at byte 7
        'error':   0x1E,  # Error propagation
        'ordered': 0x4B,  # Ordered set
    }
    
    def __init__(self):
        # Scrambler state (58-bit LFSR)
        self.lfsr = 0x3FFFFFFFFFFFFFF  # Non-zero initial state
        self.scrambler_poly = (58, 39)  # x^58 + x^39 + 1
    
    def scramble_bit(self, bit: int) -> int:
        """
        Self-synchronizing scrambler: out = in XOR lfsr[58] XOR lfsr[39]
        """
        feedback = ((self.lfsr >> 57) ^ (self.lfsr >> 38)) & 1
        out = bit ^ feedback
        # Shift LFSR with input bit
        self.lfsr = ((self.lfsr << 1) | bit) & 0x3FFFFFFFFFFFFFF
        return out
    
    def scramble_block(self, payload: int) -> int:
        """Scramble 64-bit payload."""
        scrambled = 0
        for i in range(63, -1, -1):
            bit = (payload >> i) & 1
            scrambled_bit = self.scramble_bit(bit)
            scrambled = (scrambled << 1) | scrambled_bit
        return scrambled
    
    def encode_data_block(self, data: bytes) -> int:
        """
        Encode 8 bytes of data to 66-bit block.
        
        Returns:
            66-bit value: 2-bit sync + 64-bit scrambled payload
        """
        if len(data) != 8:
            raise ValueError("Data block must be exactly 8 bytes")
        
        # Pack bytes into 64-bit payload (big-endian)
        payload = int.from_bytes(data, 'big')
        
        # Scramble payload
        scrambled = self.scramble_block(payload)
        
        # Prepend sync header
        block = (self.SYNC_DATA << 64) | scrambled
        
        return block
    
    def encode_control_block(self, block_type: str, control_data: int = 0) -> int:
        """
        Encode a control block (contains at least one control character).
        
        Args:
            block_type: Type of control block ('idle', 'start', etc.)
            control_data: Additional control/data bytes (56 bits)
        
        Returns:
            66-bit value: 2-bit sync + 8-bit type + 56-bit control/data
        """
        type_field = self.BLOCK_TYPES.get(block_type, 0x00)
        payload = (type_field << 56) | (control_data & 0x00FFFFFFFFFFFFFF)
        
        # Scramble payload
        scrambled = self.scramble_block(payload)
        
        # Prepend sync header
        block = (self.SYNC_CONTROL << 64) | scrambled
        
        return block
    
    def format_block(self, block: int) -> str:
        """Format 66-bit block for display."""
        sync = (block >> 64) & 0x3
        payload = block & 0xFFFFFFFFFFFFFFFF
        return f"[{sync:02b}] {payload:016X}"
 
 
# Demonstration
if __name__ == "__main__":
    encoder = Encoder64B66B()
    
    print("64B/66B Encoding Demonstration")
    print("=" * 60)
    
    # Encode data block
    data = bytes([0x55, 0xAA, 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC])
    block = encoder.encode_data_block(data)
    print(f"Data: {data.hex().upper()}")
    print(f"Block: {encoder.format_block(block)}")
    
    # Encode idle block
    idle_block = encoder.encode_control_block('idle')
    print(f"\nIdle block: {encoder.format_block(idle_block)}")
    
    # Encode start block
    start_block = encoder.encode_control_block('start')
    print(f"Start block: {encoder.format_block(start_block)}")

256B/257B and 512B/513B Encoding

Extreme Efficiency for 100G+ Lanes:

As lane rates increased to 100G+, even 64B/66B's 3% overhead became significant. Newer standards use larger block sizes:

Encoding	Efficiency	Overhead	Primary Use
8B/10B	80.00%	25.00%	1G/10G legacy
64B/66B	96.97%	3.03%	10G/25G/40G
256B/257B	99.61%	0.39%	100G/400G*
512B/513B	99.80%	0.20%	Emerging

*Often used in conjunction with additional FEC framing.

256B/257B Structure:

Similar to 64B/66B, but with 4× larger blocks:

1-bit sync header
256-bit payload
Payload contains four 64B/66B-style blocks (transcoded)

RS-FEC Interaction:

At 100G+ speeds, Reed-Solomon FEC is applied after encoding:

RS(544,514) for 100G/400G
Adds FEC overhead (~6%)
Combined efficiency: 256B/257B × RS ≈ 93.5%

Why Block Size Matters

Larger Blocks = Higher Efficiency:

Overhead = sync_bits / block_bits

64B/66B:  2/66 = 3.03%
256B/257B: 1/257 = 0.39%
512B/513B: 1/513 = 0.20%

Larger Blocks = Higher Latency:

Block encoding introduces alignment latency:

64B/66B at 25G: 2.64 ns per block
256B/257B at 100G: 2.57 ns per block

For latency-sensitive applications (HPC, trading), this becomes significant.

The Encoding-FEC Interaction

Forward Error Correction: Enabling Imperfect Transmission

Why FEC Became Mandatory

The SNR Budget Crisis:

As speeds increase, the available signal-to-noise ratio decreases:

Higher frequencies = more cable/connector loss
PAM-4 = 9.5 dB penalty vs NRZ
Smaller features = more device noise
Higher density = more crosstalk

Result: 100G PAM-4 systems operate with raw BER of ~10⁻⁴ (1 error per 10,000 bits). Without FEC, a 100 Gbps link would see 10 million errors per second!

Reed-Solomon FEC in Ethernet

RS(544,514) - The Workhorse Code:

IEEE 802.3 specifies Reed-Solomon FEC for high-speed Ethernet:

Parameter	Value	Meaning
n (codeword length)	544 symbols	Total symbols per block
k (data symbols)	514 symbols	User data capacity
t (correction capability)	15 symbols	Max correctable errors
Symbol size	10 bits	Each symbol is 10 bits
Overhead	5.8%	(544-514)/514
Coding gain	~6 dB	Equivalent SNR improvement

How It Works:

Interleaving: Data is spread across multiple FEC codewords to disperse burst errors
Encoding: Parity symbols calculated using Galois field arithmetic
Transmission: Data + parity sent over the channel
Syndrome Calculation: Receiver computes error indicators
Error Correction: Up to 15 symbol errors per codeword corrected
Deinterleaving: Original data order restored

FEC Performance: Raw BER to Post-FEC BER
Raw BER (Input)	Post-FEC BER	Reduction Factor	Viable?
1e-3	~1e-6	1,000×	Marginal
1e-4	~1e-12	10⁸×	≈Good
1e-5	~1e-15	10¹⁰×	Excellent
1e-6	<1e-18	10¹²×	Exceeds measurement

The FEC Cliff

FEC Types in High-Speed Networking

KR-FEC (Firecode):

Simple FEC for 10GBASE-KR, 40GBASE-KR4
RS(2112, 2080) - weak correction capability
Corrects 1 symbol error per 2112 symbols
Low latency (~100 ns)
Adequate for NRZ signaling

KP-FEC (RS-FEC):

Stronger FEC for 25G+ PAM-4
RS(544, 514) over GF(2¹⁰)
Corrects up to 15 symbol errors per codeword
Higher latency (~70-100 ns)
Mandatory for PAM-4 operation

CFEC (Concatenated FEC):

Even stronger FEC for long-reach optics
Inner code (RS) + Outer code (BCH or LDPC)
Corrects raw BER up to ~10⁻²
Higher latency (~400+ ns)
Used in coherent optics (400ZR, etc.)

FEC and Latency

FEC Latency Components:

Stage	Latency	Notes
Encoding	~10 ns	Parity calculation
Serializing	~20 ns	Block assembly
Deserializing	~20 ns	Symbol extraction
Syndrome	~15 ns	Error detection
Correction	~30 ns	Error location & fix
Total	~100 ns	Adds to link latency

For ultra-low-latency applications (HFT, HPC):

Some links operate in 'FEC bypass' mode
Higher BER tolerance required
Limited to short, high-quality channels

FEC Deployment Considerations

•PAM-4 Requirement: RS-FEC is mandatory for all PAM-4 links; NRZ may operate without FEC on short reaches
•Latency Trade-off: Stronger FEC codes introduce more latency; choose based on application needs
•Power Consumption: FEC encoders/decoders consume significant power in high-speed SerDes; ~1-2W typical
•Interoperability: FEC type and parameters must match at both ends; IEEE 802.3 specifies exactly
•Monitoring: FEC corrected/uncorrected error counts are key health metrics for link monitoring
•Margin Estimation: Pre-FEC BER indicates actual channel quality; post-FEC BER shows user experience

Modern Transceiver Architecture

Pluggable Transceiver Evolution

Pluggable Transceiver Form Factor Evolution
Form Factor	Speed	Power	Encoding Era
SFP	1-10G	1W	8B/10B
SFP+	10G	1.5W	64B/66B
SFP28	25G	2W	64B/66B + KR-FEC
QSFP+	40G	3.5W	64B/66B (4×10G)
QSFP28	100G	4.5W	256B/257B + RS-FEC
QSFP56	200G	7W	PAM-4 + RS-FEC
QSFP-DD	400G	14W	PAM-4 + RS-FEC
OSFP	400-800G	20W	PAM-4 + CFEC

Internal Architecture: 400G QSFP-DD

Block Diagram:

┌─────────────────────────────────────────────────────────────────┐
│                        QSFP-DD 400G Module                     │
├─────────────────────────────────────────────────────────────────┤
│                                                                 │
│  ┌───────┐   ┌─────────┐   ┌─────────┐   ┌─────────┐   ┌─────┐│
│  │ Cage  │   │ Host    │   │ Retimer/│   │ Laser   │   │Fiber││
│  │ I/F   │◄─►│ SerDes  │◄─►│ DSP     │◄─►│ Driver  │◄─►│ I/F ││
│  │8×100G │   │ (CTLE   │   │ (FEC,   │   │ (EML or │   │ MPO ││
│  │PAM-4  │   │  DFE)   │   │ gearbox)│   │ VCSEL)  │   │ 8ch ││
│  └───────┘   └─────────┘   └─────────┘   └─────────┘   └─────┘│
│                                                                 │
│  ┌────────────────────────────────────────────────────────────┐│
│  │                  Power & Thermal Management                 ││
│  │   14W TDP | 70°C max case temp | Active cooling support   ││
│  └────────────────────────────────────────────────────────────┘│
└─────────────────────────────────────────────────────────────────┘

Component Functions:

1. Host SerDes (on switch ASIC):

Receives 8×100G PAM-4 electrical signals from module
Performs CTLE (Continuous Time Linear Equalizer)
DFE (Decision Feedback Equalizer)
CDR (Clock and Data Recovery)

2. Retimer/DSP (in module):

Regenerates signal for long module traces
FEC encoding/decoding
Gearbox: translates host lanes to optical lanes (e.g., 8×100G → 4×100G)
PAM-4 to NRZ conversion if needed for optics

3. Laser Driver:

EML (Electro-absorption Modulated Laser) for long reach
DML (Directly Modulated Laser) for short reach
VCSEL (Vertical Cavity Surface Emitting Laser) for MMF

4. Fiber Interface:

MPO-12 or MPO-16 connector for parallel optics
LC duplex for single-lane coherent optics

Converting Mermaid diagram...

DSP Power and Complexity

The DSP Dilemma:

Modern transceivers contain sophisticated DSPs that consume significant power:

Function	Power (approx)	Why Needed
ADC (8× 100G)	2W	PAM-4 symbol detection
Equalization	3W	Channel compensation
FEC Decode	2W	Error correction
Clock Recovery	1W	Timing extraction
FEC Encode	1W	Parity generation
DAC (8× 100G)	2W	PAM-4 generation
Control/Other	3W	Management, thermal
Total	~14W	Module TDP

The Industry Response:

Linear Drive Optics: Eliminate DSP by using higher-quality lasers and shorter reaches
Co-packaged Optics: Integrate optics directly on switch ASIC, eliminating module DSP
Advanced Process Nodes: 7nm and 5nm DSPs reduce power significantly
LPO (Low Power Optics): Simplified modules for short data center reaches

The Gearbox Concept

Emerging Technologies: Beyond 800 Gbps

800G and 1.6T Ethernet

IEEE 802.3df (2024+) - 800G/1.6T Ethernet:

Speed	Lane Configuration	Encoding	Status
800G	8×100G PAM-4	256B/257B + RS	Ratified
800G	4×200G PAM-4	256B/257B + RS	In development
1.6T	8×200G PAM-4	TBD	Study group
1.6T	16×100G PAM-4	256B/257B + RS	Proposed

Key Challenges for 200G/Lane:

106.25 GBaud symbol rate
Channel bandwidth requirements exceed current copper/PCB limits
Requires either:
- Higher modulation (PAM-6/PAM-8)
- Advanced FEC with higher coding gain
- Shorter reaches
- New materials (low-loss laminates)

PAM-6 and PAM-8 Modulation

Beyond PAM-4:

Modulation	Levels	Bits/Symbol	SNR Penalty vs PAM-4
PAM-4	4	2	Reference
PAM-6	6	2.58	+4 dB
PAM-8	8	3	+7 dB
PAM-16	16	4	+14 dB

Current Research:

PAM-6/PAM-8 for electrical backplanes
Enables higher throughput without increased bandwidth
Requires even more powerful FEC (LDPC, Turbo codes)
DSP complexity and power increase significantly

Coherent Optics in Data Centers

The Coherent Revolution:

Coherent detection, long used in telecom, is entering the data center:

Coherent vs Direct Detect:

Property	Direct Detect	Coherent
Detection	Intensity	Phase & amplitude
Modulation	PAM	QAM (16-QAM, 64-QAM)
Dimensions	1 (intensity)	4 (I, Q, polarization)
Spectral efficiency	~1 bit/Hz	4-8 bits/Hz
DSP complexity	Moderate	Very high
Reach	<10 km	100+ km

400ZR and 400ZR+:

Coherent optics in QSFP-DD/OSFP form factor
400 Gbps over 80+ km single-mode fiber
16-QAM modulation on two polarizations
CFEC with soft-decision decoding

Data Center Interconnect (DCI):

Connects data centers 10-100 km apart
Coherent optics avoid regeneration
Single fiber pair carries 400 Gbps
Future: 800 Gbps, 1.2 Tbps coherent pluggables

Co-Packaged Optics (CPO)

The Final Integration Frontier:

CPO integrates optical engines directly on the switch ASIC package:

┌─────────────────────────────────────────────┐
│               Switch Package                │
│  ┌─────────────────────────────────────┐   │
│  │           Switch ASIC               │   │
│  │      (51.2 Tbps switching)          │   │
│  └──────────────┬──────────────────────┘   │
│                 │ Very short traces        │
│  ┌──────────────┴──────────────────────┐   │
│  │      Co-Packaged Optical Engine     │   │
│  │  (32× 400G = 12.8 Tbps I/O)         │   │
│  └─────────────────────────────────────┘   │
│                 │ Fiber ribbon             │
└─────────────────┼─────────────────────────┘
                  ↓
              Fiber plant

Advantages:

Eliminates module-to-ASIC traces (major power savings)
Reduces latency (no retimer needed)
Enables higher bandwidth density
Lower cost per Gbps at scale

Challenges:

Reliability (no hot-swap at CPO level)
Thermal management (optics on hot ASIC)
Ecosystem development (new manufacturing)

Future Directions

•Higher Modulation: PAM-6, PAM-8 for electrical; 64-QAM, 256-QAM for coherent optics
•Stronger FEC: LDPC and Turbo codes with soft-decision decoding approaching Shannon limit
•Co-Packaged Optics: Integration of optics on switch ASICs for >25 Tbps switch capacity
•Silicon Photonics: CMOS-compatible optical components for cost reduction
•Machine Learning: ML-based equalization and CDR for complex channels
•Photonic Computing: Optical domain processing to reduce electrical DSP power

The Shannon Limit

Summary: Multilevel Coding in Modern Networks

Let's consolidate the essential knowledge from this comprehensive module:

Core Concepts to Remember

•Multilevel Signaling Principle: Using L voltage levels encodes log₂(L) bits per symbol, trading noise margin for bandwidth efficiency
•Block Coding Trade-offs: mB/nB codes add redundancy (n>m) to guarantee clock recovery, DC balance, and error detection
•PAM-4 Revolution: Doubles throughput per baud but requires FEC due to 9.5 dB SNR penalty vs NRZ
•FEC Necessity: Modern links operate at raw BER ~10⁻⁴; RS-FEC (~10⁻¹² post-FEC) is mandatory beyond 25 Gbps
•Efficiency Evolution: 8B/10B (80%) → 64B/66B (97%) → 256B/257B (99.6%) enables higher net throughput
•System Integration: Modern transceivers combine modulation, encoding, FEC, and DSP into integrated signal chains

Module Quick Reference: Encoding Schemes
Scheme	Efficiency	DC Balance	Primary Era
MLT-3	80% (w/4B5B)	Good	100M (1995)
2B1Q	100%*	Scrambled	ISDN/DSL (1988)
4B/5B	80%	Poor	100M/FDDI (1990)
8B/10B	80%	Guaranteed	1G/FC (1998)
64B/66B	97%	Scrambled	10G/25G (2002)
256B/257B	99.6%	Scrambled	100G+ (2017)
PAM-4 (signaling)	2 bits/sym	N/A	50G+ (2017)

*2B1Q efficiency is 100% for the line code itself; overhead comes from framing.

The Engineering Mindset:

Throughout this module, you've seen that every encoding decision involves trade-offs:

Bandwidth efficiency vs. noise immunity
DC balance vs. implementation complexity
Error detection vs. overhead
Latency vs. error correction strength

What You Now Understand

•Why MLT-3 enabled Fast Ethernet over Cat 5
•How 2B1Q doubled ISDN efficiency
•Why 4B/5B + MLT-3 is a perfect pair
•How 8B/10B guarantees DC balance
•Why PAM-4 + FEC is essential for 100G+
•How modern transceivers integrate everything

Skills You Can Apply

•Evaluate encoding schemes for new designs
•Interpret eye diagrams and signal quality
•Understand FEC metrics and limits
•Troubleshoot physical layer issues
•Specify transceiver requirements
•Anticipate future technology evolution

Module Complete: Multilevel Coding Mastered

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