Process Control Block (PCB)

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// Why flags must be preserved exactly
 
int compare_values(int a, int b) {
    // Assembly perspective: cmp sets flags
    // cmp eax, ebx    ; computes a - b, sets ZF, SF, CF, OF
    
    if (a < b) {       // Uses SF and OF (signed comparison)
        return -1;
    } else if (a > b) { // Uses flags again
        return 1;
    } else {           // Uses ZF
        return 0;
    }
}
 
// If context switch happens between CMP and conditional jump:
//
//   cmp  eax, ebx     ; Flags set here
//   <--- CONTEXT SWITCH HAPPENS HERE --->
//   jl   less_than    ; Uses flags from cmp
//
// If flags weren't restored, the jump uses wrong flags!
// Process would take wrong branch, corrupting execution.
 
// Kernel must save exact flags state:
struct context_switch_frame {
    uint64_t rflags;  // Saved flags register
    uint64_t rip;     // Program counter
    uint64_t rsp;     // Stack pointer
    // ... other registers
};

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// Lazy FPU context switching (simplified Linux approach)
 
// Per-CPU: Which task owns the FPU?
DEFINE_PER_CPU(struct task_struct *, fpu_owner);
 
// On context switch - DON'T save FPU
void context_switch(struct task_struct *prev, struct task_struct *next) {
    // Save integer registers (always)
    save_integer_context(prev);
    
    // For FPU: just disable it
    if (cpu_has_fpu()) {
        // Set CR0.TS (Task Switched) bit
        // Any FPU access will now cause #NM (Device Not Available)
        disable_fpu_access();
    }
    
    // Switch address space and integer context
    switch_mm(next);
    restore_integer_context(next);
}
 
// Device Not Available exception handler
void do_device_not_available(struct pt_regs *regs) {
    struct task_struct *current_task = current;
    struct task_struct *fpu_owner_task = this_cpu_read(fpu_owner);
    
    // Save previous owner's FPU state (if different from current)
    if (fpu_owner_task && fpu_owner_task != current_task) {
        save_fpu_state(&fpu_owner_task->fpu_state);
    }
    
    // Restore current task's FPU state (or initialize if never used)
    if (current_task->fpu_initialized) {
        restore_fpu_state(&current_task->fpu_state);
    } else {
        init_fpu_state();
        current_task->fpu_initialized = true;
    }
    
    // Mark current as FPU owner
    this_cpu_write(fpu_owner, current_task);
    
    // Clear CR0.TS to enable FPU access
    enable_fpu_access();
    
    // Return from exception - faulting instruction will be retried
}
 
// Actual save/restore using FXSAVE/FXRSTOR or XSAVE/XRSTOR
void save_fpu_state(struct fpu_state *state) {
    // XSAVE saves all extended state (SSE, AVX, AVX-512, etc.)
    // based on XCR0 register configuration
    asm volatile("xsave %0" : "=m"(state->xsave_area) : "a"(-1), "d"(-1));
}
 
void restore_fpu_state(struct fpu_state *state) {
    asm volatile("xrstor %0" : : "m"(state->xsave_area), "a"(-1), "d"(-1));
}

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// Address space switching on x86-64
 
// The mm_struct contains the page table pointer
struct mm_struct {
    pgd_t *pgd;           // Top-level page table (PML4)
    unsigned long cr3;     // Pre-computed CR3 value
    unsigned int pcid;     // Process Context ID (for TLB tagging)
    // ... other fields
};
 
// Switch address space
void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm) {
    if (prev_mm == next_mm) {
        // Same address space - no switch needed (e.g., threads)
        return;
    }
    
    // Build CR3 value: page table base + PCID
    unsigned long new_cr3 = next_mm->cr3;
    
    if (cpu_has_pcid()) {
        // Include PCID to avoid TLB flush
        new_cr3 |= next_mm->pcid;
        
        // Set bit 63 to NOT flush TLB entries with this PCID
        new_cr3 |= (1UL << 63);
    }
    
    // The actual switch - this is expensive!
    write_cr3(new_cr3);
    
    // Update per-CPU tracking
    this_cpu_write(current_mm, next_mm);
}
 
// Inline assembly for CR3 access
static inline void write_cr3(unsigned long val) {
    asm volatile("mov %0, %%cr3" : : "r"(val) : "memory");
}
 
static inline unsigned long read_cr3(void) {
    unsigned long val;
    asm volatile("mov %%cr3, %0" : "=r"(val));
    return val;
}
 
// TLB impact:
// Without PCID: write_cr3 flushes ALL TLB entries
//               Next memory accesses suffer TLB misses
//               Each miss = page table walk = 4 memory accesses
// With PCID:    Only flush entries with matching PCID
//               Other processes' entries remain cached
//               Significant performance improvement

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// Complete CPU context for context switching (x86-64 example)
 
// Integer register context
struct integer_context {
    // General-purpose registers
    uint64_t rax;
    uint64_t rbx;
    uint64_t rcx;
    uint64_t rdx;
    uint64_t rsi;
    uint64_t rdi;
    uint64_t rbp;
    uint64_t rsp;
    uint64_t r8;
    uint64_t r9;
    uint64_t r10;
    uint64_t r11;
    uint64_t r12;
    uint64_t r13;
    uint64_t r14;
    uint64_t r15;
    
    // Program counter and flags
    uint64_t rip;
    uint64_t rflags;
    
    // Segment selectors (usually unchanged in 64-bit mode)
    uint16_t cs;
    uint16_t ss;
    uint16_t ds;
    uint16_t es;
    uint16_t fs;
    uint16_t gs;
    
    // FS/GS base addresses (for thread-local storage)
    uint64_t fs_base;
    uint64_t gs_base;
};
// Size: approximately 160 bytes
 
// FPU/SIMD context (XSAVE area)
// Layout depends on CPU features enabled
struct fpu_context {
    // Legacy x87 + SSE state (FXSAVE format)
    uint16_t fcw;         // FPU control word
    uint16_t fsw;         // FPU status word
    uint8_t  ftw;         // FPU tag word (abridged)
    uint8_t  reserved1;
    uint16_t fop;         // FPU opcode
    uint64_t fip;         // FPU instruction pointer
    uint64_t fdp;         // FPU data pointer
    uint32_t mxcsr;       // SIMD control/status
    uint32_t mxcsr_mask;
    
    // x87 FPU registers (ST0-ST7)
    uint8_t st_space[128];  // 8 × 16 bytes (80-bit padded)
    
    // SSE registers (XMM0-XMM15)
    uint8_t xmm_space[256]; // 16 × 16 bytes
    
    // XSAVE header (for extended state)
    uint64_t xstate_bv;     // State components present
    uint64_t xcomp_bv;      // State components format
    uint8_t reserved2[48];
    
    // Extended state (AVX, AVX-512, etc.)
    // Size varies based on CPU and enabled features
    // Can be 2KB+ for AVX-512
    uint8_t extended_state[0];  // Variable-length
};
// Size: 512+ bytes (up to 2KB+ for AVX-512)
 
// Combined context in PCB
struct task_struct {
    // ... process identification fields
    
    // CPU context
    struct integer_context cpu_context;
    
    // FPU/SIMD context (dynamically allocated based on CPU features)
    struct fpu_context *fpu;
    
    // Address space
    unsigned long cr3;          // Page table pointer
    struct mm_struct *mm;       // Memory management
    
    // Debug registers (only if debugging active)
    unsigned long debugreg[8];
    
    // ... scheduling, files, signals, etc.
};
 
// Typical total context size breakdown:
// - Integer registers + RIP + RFLAGS: ~160 bytes
// - SSE state (FXSAVE): ~512 bytes  
// - AVX state: +256 bytes
// - AVX-512 state: +2048 bytes
// - Miscellaneous: ~64 bytes
//
// Total: ~750 bytes (SSE) to ~3000 bytes (AVX-512)

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// Measuring context switch time (simplified benchmark)
 
#include <stdio.h>
#include <unistd.h>
#include <sys/wait.h>
#include <time.h>
 
#define ITERATIONS 100000
 
int main() {
    int pipe1[2], pipe2[2];
    pipe(pipe1);
    pipe(pipe2);
    
    pid_t pid = fork();
    
    if (pid == 0) {
        // Child: ping-pong through pipes
        char c;
        for (int i = 0; i < ITERATIONS; i++) {
            read(pipe1[0], &c, 1);   // Wait for parent
            write(pipe2[1], &c, 1);  // Signal parent
            // Each iteration = 2 context switches
        }
        _exit(0);
    }
    
    // Parent: measure ping-pong time
    struct timespec start, end;
    char c = 'x';
    
    clock_gettime(CLOCK_MONOTONIC, &start);
    
    for (int i = 0; i < ITERATIONS; i++) {
        write(pipe1[1], &c, 1);  // Signal child
        read(pipe2[0], &c, 1);   // Wait for child
    }
    
    clock_gettime(CLOCK_MONOTONIC, &end);
    
    wait(NULL);
    
    double elapsed_ns = (end.tv_sec - start.tv_sec) * 1e9 + 
                        (end.tv_nsec - start.tv_nsec);
    double per_switch = elapsed_ns / (ITERATIONS * 2);
    
    printf("Context switches: %d\n", ITERATIONS * 2);
    printf("Time per switch: %.1f ns\n", per_switch);
    
    // Typical results:
    // - Same CPU core: ~1-2 μs (includes pipe overhead)
    // - Different cores: ~3-5 μs
    // Pure context switch (no pipe): ~200-500 ns
    
    return 0;
}