Time Division Multiplexing (TDM)

When AT&T engineers designed the T-carrier system in the early 1960s, they faced a critical decision: how should time slots be assigned to sources? They could let sources compete for slots dynamically, or they could pre-assign slots in a fixed pattern that never changes.

They chose the latter approach—Synchronous TDM—and this decision shaped global telecommunications for the next six decades.

Synchronous TDM assigns each source a permanent, predetermined time slot that repeats in every frame. Whether a source has data to send or not, its slot is reserved and transmitted. This creates a perfectly predictable, deterministic system where you can always know exactly when a particular source's data will arrive.

The Telephone Network Paradigm:

This approach was perfect for telephony. A phone call, once established, requires continuous bidirectional communication for the duration of the call. The voice signal is sampled 8,000 times per second, and each sample must be delivered with consistent timing. Synchronous TDM guarantees this consistency because every 125 microseconds, without fail, the designated slot carries voice data.

Synchronous TDM operates on several fundamental principles that distinguish it from other multiplexing approaches and define its operational characteristics.

Principle 1: Fixed Slot Assignment

Each input source is assigned a specific slot position within the frame, and this assignment remains constant for the duration of the connection. If Source A is assigned Slot 3, then Slot 3 in every frame contains data from Source A (or empty padding if A has nothing to send).

This fixed assignment eliminates the need for addressing overhead within the data stream. The receiver doesn't need to be told "this data is for Channel A"—it knows that Slot 3 is always Channel A's slot.

Principle 2: Constant Frame Rate

The frame rate is fixed and synchronized to the sampling rate of the sources. For PCM voice at 8 kHz sampling, frames are generated exactly 8,000 times per second, creating the characteristic 125 μs frame duration.

$$T_{frame} = \frac{1}{\text{Sampling Rate}} = \frac{1}{8000\text{ Hz}} = 125\text{ μs}$$

Principle 3: Synchronous Operation

Both transmitter and receiver operate from the same master clock or from clocks that are traceable to a common reference. This ensures that frames are generated and consumed at exactly the same rate, preventing buffer overflow or underflow.

Principle 4: Implicit Addressing

Because slot positions are fixed and known to both ends, data within a frame carries no explicit address. The position (slot number) is the address. This eliminates addressing overhead entirely, making synchronous TDM extremely bandwidth-efficient for constant-rate sources.

Consider the contrast:

Principle 5: Deterministic Delay

The delay through a synchronous TDM system is completely predictable. A sample entering the multiplexer experiences a delay of at most one frame duration before transmission (waiting for its slot), plus propagation delay, plus demultiplexer processing. This determinism is essential for real-time applications like voice.

$$D_{max} = T_{frame} + T_{propagation} + T_{processing}$$

For a T1 system spanning 1,000 km:

• Frame delay: ≤ 125 μs
• Propagation: ~5 ms (at ~2×10⁸ m/s)
• Processing: ~10 μs
• Total: ~5.14 ms (predictable to within microseconds)

The frame is the fundamental unit of synchronous TDM. Its structure determines system capacity, overhead, and operational characteristics. Designing an optimal frame involves balancing multiple competing requirements.

Generic Frame Structure:

┌─────────────────────────────────────────────────────────────────┐
│                       TDM FRAME                                 │
├───────┬────────┬────────┬────────┬─────┬────────┬──────────────┤
│ Sync/ │ Slot 1 │ Slot 2 │ Slot 3 │ ... │ Slot N │ Signaling/   │
│ Frame │ (Ch 1) │ (Ch 2) │ (Ch 3) │     │ (Ch N) │ Control      │
│ Bits  │        │        │        │     │        │ (optional)   │
└───────┴────────┴────────┴────────┴─────┴────────┴──────────────┘

Key Frame Components:

Frame Design Tradeoffs:

Multiframe Structures:

For applications requiring more signaling capacity or longer cyclic patterns, multiple frames are grouped into a multiframe or superframe:

• T1 Superframe (SF): 12 frames, used for robbed-bit signaling
• T1 Extended Superframe (ESF): 24 frames, adds CRC and data link
• E1 Multiframe: 16 frames, provides signaling for all 30 data channels

The multiframe structure allows spreading signaling and control information across multiple frames, reducing per-frame overhead while maintaining adequate signaling capacity.

Synchronization is the lifeblood of synchronous TDM. Without precise timing alignment, the receiver cannot correctly interpret the incoming bit stream—it won't know where frames begin, which bits belong to which slot, or which slot belongs to which channel.

Types of Synchronization:

1. Bit Synchronization: The receiver must sample the incoming signal at exactly the right moments to correctly detect each bit. This requires knowing the transmitter's bit clock frequency and phase.

• Implementation: Phase-Locked Loops (PLLs) that extract clock from signal transitions
• Accuracy Required: Within a fraction of a bit period (typically <10% of bit duration)
• Recovery Method: Analysis of signal transitions; more transitions = easier recovery

2. Frame Synchronization: The receiver must identify where each frame begins. This is accomplished by detecting the framing pattern.

• Implementation: Correlators that match incoming bits against known frame pattern
• Acquisition Time: May require observing multiple frames to confirm lock
• False Lock Risk: Random data might occasionally match the frame pattern

3. Multiframe Synchronization: For systems using multiframes, the receiver must identify the multiframe boundary.

• Implementation: Multiframe alignment word (MAW) or pattern rotation
• Purpose: Enables signaling channel identification and CRC checking

4. Network Synchronization: In networks with multiple TDM nodes, all nodes must derive timing from a common reference to prevent timing slips.

• Implementation: Hierarchical timing distribution from stratum clocks
• Consequence of Failure: Periodic frame slips causing audible clicks or data errors

The Frame Synchronization Algorithm:

STATE: SEARCH
    1. Shift bits into buffer
    2. Compare buffer against frame pattern
    3. If match: transition to VERIFY, reset miss counter
    4. If no match: continue searching

STATE: VERIFY
    1. Wait one frame period
    2. Check if frame pattern appears at expected position
    3. If match: increment verify count
       If verify count ≥ threshold: transition to SYNC
    4. If no match: transition back to SEARCH

STATE: SYNC (normal operation)
    1. Process frame data normally
    2. Periodically verify frame pattern
    3. If pattern missing: increment miss counter
       If miss counter ≥ threshold: transition to SEARCH
    4. If pattern present: reset miss counter

This state machine prevents false synchronization on random data matches and provides hysteresis to avoid dropping sync on single bit errors.

In synchronous TDM, slot assignment is a configuration decision made when connections are established, not a dynamic real-time process. Understanding how slots are assigned and managed reveals the operational model of traditional telecommunications.

Connection-Oriented Assignment:

When a call is placed in a TDM-based telephone network:

1. Call Setup Request: User dials a number; signaling protocols (SS7) determine the path
2. Path Selection: Network finds available slots on each link along the path
3. Slot Binding: A specific slot is reserved on each TDM link for this call
4. Connection Map Creation: Each switch stores mapping: (incoming slot) → (outgoing slot)
5. Call Proceeds: Voice samples flow through the dedicated slot path
6. Teardown: When call ends, slots are released and become available

The Cross-Connect Concept:

At each TDM switch, a time-slot interchange (TSI) or cross-connect maps incoming slots to outgoing slots. This is the TDM equivalent of a routing table:

Incoming Link A          Cross-Connect          Outgoing Link B
┌─────────────┐         ┌───────────┐         ┌─────────────┐
│ Slot 1 ────────────▶  │ A1 → B5   │ ────▶   │ Slot 5      │
│ Slot 2 ────────────▶  │ A2 → B12  │ ────▶   │ Slot 12     │
│ Slot 3      │         │ A3 → B3   │         │ Slot 3      │
│    ...      │         │    ...    │         │    ...      │
└─────────────┘         └───────────┘         └─────────────┘

The cross-connect can also switch between frames at different rates through a process called add-drop multiplexing, extracting specific channels from a higher-rate stream.

Understanding the efficiency of synchronous TDM requires examining how the total bandwidth is distributed among payload, overhead, and—crucially—idle capacity.

Bandwidth Allocation Components:

$$B_{total} = B_{payload} + B_{overhead} + B_{idle}$$

Where:

• $B_{payload}$ = Useful user data
• $B_{overhead}$ = Framing, synchronization, signaling
• $B_{idle}$ = Unused capacity in allocated but inactive slots

T1 Example: Fully Loaded

T1 Example: Half Loaded (12 active channels)

Efficiency Under Different Traffic Patterns:

The efficiency of synchronous TDM depends heavily on the nature of the traffic:

Why This Matters:

The efficiency mismatch between synchronous TDM and data traffic explains the telecommunications industry's evolution:

1. 1960s-1980s: Voice dominated; TDM efficiency was excellent
2. 1990s: Data traffic grew; TDM inefficiency became painful
3. 2000s: Statistical TDM, ATM, and packet switching gained ground
4. 2010s+: IP dominates, but TDM persists for legacy and deterministic applications

The quest for better efficiency led directly to Statistical TDM (covered next) and ultimately to the packet-switched paradigm.

Synchronous TDM systems must handle various error conditions while maintaining service continuity. The error handling mechanisms reveal the robustness engineering behind telecommunications reliability.

Error Categories:

1. Bit Errors: Random corruption of bits due to noise, interference, or equipment problems.

Detection: CRC checks (in ESF/E1), parity bits Impact: Corrupted voice samples (clicks, pops) or data errors Recovery: Usually none at TDM layer; higher layers may request retransmission

2. Frame Slips: Occur when transmitter and receiver clocks differ slightly, causing buffer overflow or underflow.

Types:

• Controlled slip: Entire frame dropped or repeated under controlled conditions
• Uncontrolled slip: Arbitrary data loss due to buffer overflow

Impact: Audible click in voice; significant disruption in data Prevention: Stringent clock accuracy requirements; slip buffers

3. Loss of Frame (LOF): Receiver cannot locate frame boundaries.

Causes: Heavy bit errors, equipment failure, cable damage Detection: Framing pattern not found within timeout Impact: Complete loss of all channels Recovery: Re-acquisition of frame sync; may take milliseconds to seconds

4. Loss of Signal (LOS): No signal detected on the incoming line.

Causes: Cable cut, equipment power loss, interface failure Detection: Signal amplitude below threshold Impact: All channels fail Recovery: Depends on cause; may trigger protection switching

5. Alarm Indication Signal (AIS): A special pattern transmitted downstream when the upstream detects a failure.

Purpose: Informs downstream equipment that upstream is aware of the problem; prevents false alarms from propagating Pattern: All-ones (1111....) continuously Usage: Equipment seeing AIS knows to suppress its own alarms

Error Monitoring Metrics:

PDH and SDH/SONET systems track performance through standardized metrics:

Deploying and maintaining synchronous TDM systems involves numerous practical considerations that textbook descriptions often omit. Understanding these real-world factors is essential for network engineers working with TDM infrastructure.

Clock Source Selection:

A TDM network must derive timing from a reliable source. The options, in order of preference:

1. Primary Reference Source (PRS): Stratum 1 atomic clock, ± 1×10⁻¹¹ accuracy
2. Synchronization Supply Unit (SSU): Local buffer that holds timing if upstream fails
3. Building Integrated Timing Supply (BITS): Distributes timing within a facility
4. Line Timing: Derive clock from received signal (last resort; propagates jitter)

Cable and Connector Considerations:

Testing and Troubleshooting:

Common Troubleshooting Scenarios:

1. Intermittent errors: Often caused by loose connectors, marginal cable, or external interference. Check physical layer first.

2. One-way audio: Cross-connect misconfiguration; incoming and outgoing slots not properly paired.

3. Clicks every few minutes: Timing slips; investigate clock sources and distribution.

4. Complete outage after change: Verify framing format match (ESF vs. SF, CRC4 vs. non-CRC4); mismatched formats cause frame loss.

5. Gradual degradation: Cable aging, water ingress, or creeping interference. Compare current BERT results to installation baseline.

We've completed a thorough examination of Synchronous TDM, the deterministic approach that built global telephony. Let's consolidate the essential knowledge:

What's Next:

Synchronous TDM excels for constant-rate traffic but struggles with bursty data sources. The telecommunications industry's answer was Statistical TDM (also called Asynchronous TDM or Statistical Multiplexing)—an approach that dynamically allocates slots based on actual demand, eliminating the empty slot problem. We'll explore how statistical TDM trades determinism for efficiency and examine its role in bridging traditional TDM and packet switching.