Analog Signals - Learning Module

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Analog-to-Digital Conversion: Bridging Two Worlds

Converting Reality to Numbers

The physical world speaks in analog—continuous voltages, pressures, temperatures, and electromagnetic waves. But computers speak in digital—discrete numbers with finite precision. The Analog-to-Digital Converter (ADC) is the translator between these two domains, converting the infinite richness of analog signals into the finite precision of binary numbers.

This conversion is not merely a technical detail—it is perhaps the most consequential transformation in modern technology. Every digital photograph, every MP3 file, every cell phone call, every medical scan begins with an ADC capturing a slice of the analog world. The quality, speed, and precision of this conversion fundamentally determine what digital systems can achieve.

In this page, we explore the complete ADC process: sampling, quantization, and encoding—the three steps that transform continuous signals into digital representations.

Learning Objectives

By the end of this page, you will: (1) Understand the sampling process and the Nyquist-Shannon sampling theorem, (2) Master quantization—resolution, error, and dynamic range, (3) Learn about common ADC architectures and their tradeoffs, (4) Understand practical limitations including aperture jitter and noise, (5) Be able to select appropriate ADC specifications for communication applications.

The Three Steps of A-to-D Conversion

Analog-to-digital conversion transforms a continuous-time, continuous-amplitude signal into a discrete-time, discrete-amplitude representation through three distinct processes:

1. Sampling (Time Discretization):

The continuous signal is measured at regular intervals, converting a function of continuous time into a sequence of values at discrete time points. The interval between samples is the sampling period (Ts); its reciprocal is the sampling frequency (fs = 1/Ts).

Before: s(t) — value defined for all t After: s[n] = s(nTs) — values defined only at n = 0, 1, 2, ...

2. Quantization (Amplitude Discretization):

Each sampled value is approximated to the nearest value from a finite set of levels. An N-bit quantizer has 2^N possible output levels. The difference between the actual sample and the quantized value is the quantization error.

Before: Sample = 1.23456789... V (infinite precision) After: Quantized = 1.234 V (limited to N bits)

3. Encoding (Binary Representation):

Each quantized level is assigned a unique binary code. This encoding determines how the discrete levels map to bit patterns—straight binary, two's complement, offset binary, Gray code, etc.

Before: Quantized level = Level 157 (of 256) After: Binary code = 10011101

The A/D Conversion Pipeline
Stage	Input	Output	Key Parameters
Anti-Alias Filter	Analog signal (wideband)	Analog signal (bandlimited)	Cutoff frequency, filter order
Sample & Hold	Bandlimited analog	Discrete-time samples	Sampling rate, aperture jitter
Quantization	Continuous amplitude	Discrete levels	Resolution (bits), range
Encoding	Quantized levels	Binary numbers	Code type, format

The Order Matters

These three steps must occur in order. You cannot quantize before sampling (you need a fixed value to quantize). You cannot encode before quantizing (you need a discrete level to assign a code). The anti-alias filter must precede sampling (to prevent aliasing). This pipeline structure is fundamental to all ADC implementations.

Sampling and the Nyquist Theorem

Sampling converts a continuous-time signal to a discrete-time sequence. But a fundamental question arises: How fast must we sample to preserve the signal information?

The Nyquist-Shannon Sampling Theorem:

A bandlimited signal with maximum frequency fmax can be perfectly reconstructed from samples taken at rate fs > 2fmax.

The minimum sampling rate fs = 2fmax is called the Nyquist rate.

The maximum signal frequency fmax = fs/2 is called the Nyquist frequency.

Why 2× ?

A sinusoid requires at least 2 samples per cycle to be distinguished from other frequencies. With exactly 2 samples per cycle, sampling occurs at the peaks and troughs (for worst-case phase). Fewer samples create ambiguity—multiple sinusoids could produce the same samples.

Aliasing:

When a signal contains frequencies above the Nyquist frequency (fs/2), those frequencies appear as lower frequencies in the sampled data—they become 'aliases' of themselves.

A frequency f > fs/2 aliases to |f - n×fs| for some integer n.

Example: Sampling at fs = 10 kHz:

3 kHz signal → sampled correctly as 3 kHz
7 kHz signal → aliases to 3 kHz! (10 - 7 = 3)
13 kHz signal → aliases to 3 kHz! (13 - 10 = 3)

Once aliased, the original frequency cannot be recovered—the information is lost.

Anti-Aliasing Filters:

To prevent aliasing, an analog low-pass filter (the anti-aliasing filter) removes frequencies above fs/2 before sampling. This filter must have:

Passband up to the highest frequency of interest
Stopband beginning before fs/2
Sufficient attenuation to reduce out-of-band signals below quantization noise

Common Sampling Rates and Applications
Application	Sampling Rate	Nyquist Frequency	Typical Signal Bandwidth
Telephone (G.711)	8 kHz	4 kHz	300-3400 Hz voice
CD Audio	44.1 kHz	22.05 kHz	20 Hz - 20 kHz audio
DAT/DVD Audio	48 kHz	24 kHz	20 Hz - 20 kHz+ audio
Studio Audio	96 kHz	48 kHz	Extended high frequencies
Ultrasound Imaging	40 MHz	20 MHz	1-15 MHz ultrasound
Software Radio (HF)	100 MHz	50 MHz	0-30 MHz spectrum
Oscilloscope (1 GHz)	4 GS/s	2 GHz	DC to 1 GHz signals

The Practical Margin

Theory says fs > 2fmax is sufficient. Practice requires more margin: (1) Real filters have gradual rolloff, not brick-wall cutoff, (2) ADC aperture effects worsen at high frequencies, (3) Interpolation for reconstruction is easier with oversampling. Typical designs use fs = 2.5× to 4× the signal bandwidth. CD audio (44.1 kHz) allows only 10% margin above 20 kHz—pushing the limits.

Sample-and-Hold Circuits

Real ADCs take finite time to perform conversion. A sample-and-hold (S/H) circuit captures an instantaneous snapshot of the input signal and holds it constant while the ADC completes its work.

Basic Operation:

Sample Mode: A switch connects the input to a capacitor. The capacitor voltage tracks the input signal.
Hold Mode: The switch opens due to a clock edge. The capacitor retains its voltage, providing a stable value during conversion.

Key Parameters:

Acquisition Time: How long the capacitor needs in sample mode to settle to a new input value. Shorter is better for high-speed ADCs.

Aperture Delay: The delay between the sample command (clock edge) and when the switch actually opens. This is a fixed delay—predictable and compensatable.

Aperture Jitter: Random variation in when the switch opens. This is the critical specification for high-frequency signals. Jitter of tj causes SNR limit:

SNRaper = −20 log₁₀(2πf * tj)

For a full-scale sinusoid at frequency f.

Droop: In hold mode, the capacitor slowly discharges through leakage. Droop must be small compared to 1 LSB over the conversion time.

Feedthrough: In hold mode, some input signal leaks through the open switch. Feedthrough must be low enough not to corrupt the held value.

Examples:

12-bit ADC, 1 MHz input: Aperture jitter must be < 1/(2π × 10⁶ × 2¹²) ≈ 39 ps
14-bit ADC, 10 MHz input: Aperture jitter must be < 0.97 ps
Modern high-speed ADCs achieve < 100 femtosecond aperture jitter

Sample-and-Hold Performance Factors

•Acquisition bandwidth — The S/H must track signals up to the Nyquist frequency
•Hold capacitor size — Larger = lower droop but slower acquisition
•Switch quality — Low on-resistance, low off-leakage, fast transition
•Buffer amplifiers — Drive capability and settling time
•Temperature stability — Leakage increases with temperature
•Clock quality — Jitter in the sample command becomes aperture jitter

Track-and-Hold vs. Sample-and-Hold

A 'sample-and-hold' technically samples briefly and then holds. A 'track-and-hold' continuously tracks the input and holds on command. The terms are often used interchangeably, though track-and-hold more accurately describes most modern implementations. What matters is the transition from tracking to holding—that's when the critical aperture specifications apply.

Quantization: Discretizing Amplitude

Quantization maps continuous amplitude values to a finite set of discrete levels. This is where 'resolution' comes in—an N-bit ADC has 2^N possible output codes.

Key Definitions:

Full-Scale Range (FSR): The total analog input range the ADC can accept (e.g., 0-3.3V or ±1V).

Least Significant Bit (1 LSB): The smallest distinguishable voltage step:

1 LSB = FSR / 2^N

For a 12-bit ADC with 3.3V range: 1 LSB = 3.3V / 4096 ≈ 0.806 mV

Quantization Error: The difference between the actual sample and the quantized value. For uniform quantization:

-0.5 LSB ≤ error ≤ +0.5 LSB (with rounding) 0 ≤ error ≤ 1 LSB (with truncation)

Signal-to-Quantization-Noise Ratio (SQNR):

For a full-scale sinusoidal input with uniform quantization:

SQNR = 6.02N + 1.76 dB

Where N is the number of bits. Each additional bit adds ~6 dB of dynamic range.

Dynamic Range:

The ratio of the largest to smallest signal the ADC can represent:

8-bit: 48 dB + 1.76 = 49.76 dB
12-bit: 72 dB + 1.76 = 73.76 dB
16-bit: 96 dB + 1.76 = 97.76 dB
24-bit: 144 dB + 1.76 = 145.76 dB (theoretical)

Quantization Specifications by Resolution
Bits (N)	Levels (2^N)	SQNR (dB)	1 LSB (3.3V FSR)	Applications
8	256	49.9	12.9 mV	Video, basic audio, control
10	1024	61.9	3.2 mV	Video, instrumentation
12	4096	74.0	0.81 mV	Data acquisition, communications
14	16384	86.0	0.20 mV	High-quality audio, radar
16	65536	98.1	50 µV	Professional audio, precision
18	262144	110.1	12.6 µV	Scientific measurement
24	16.7M	146.2	0.20 µV	Audio mastering, seismology

Effective Number of Bits (ENOB)

Real ADCs don't achieve the theoretical SQNR. Noise, distortion, and nonlinearity reduce performance. ENOB measures actual performance: ENOB = (SINAD - 1.76) / 6.02. A '16-bit' ADC might have ENOB of only 12-14 bits at high frequencies due to aperture jitter and internal noise. Always check ENOB, not just stated resolution.

Quantization Noise and Dithering

Quantization is an inherently lossy process—some information is lost when continuous values are forced onto a finite grid. This loss manifests as quantization noise.

Characteristics of Quantization Error:

For busy, varying signals, quantization error behaves like random noise:

Uniformly distributed between -0.5 LSB and +0.5 LSB (with rounding)
Uncorrelated with the signal (for most practical signals)
White spectrum (equal power at all frequencies up to fs/2)

Total quantization noise power: σ² = (1 LSB)² / 12

RMS quantization noise: σ = 1 LSB / √12 ≈ 0.289 LSB

The Problem with Small Signals:

When signal amplitude is smaller than 1 LSB, quantization produces gross distortion—the output might be just two values switching back and forth. This is not noise-like behavior; it's severe nonlinear distortion.

Dithering:

Dither is small random noise intentionally added to the signal before quantization. This sounds counterproductive but actually improves quality:

The added noise 'randomizes' the quantization error even for small signals
Quantization error becomes uncorrelated and noise-like
After averaging or filtering, the noise averages out but signal doesn't
Resolution beyond the ADC's native bits becomes possible through oversampling

Types of Dither:

Rectangular dither: Uniform distribution, ±0.5 LSB. Decorrelates error but doesn't eliminate modulation noise.
Triangular dither: ±1 LSB amplitude (PDF is triangle-shaped). Fully randomizes and eliminates modulation noise.
Gaussian dither: Normal distribution. Natural in physical systems.

Without Dither (Small Signals)

•Harsh quantization distortion
•Correlated error (not noise-like)
•Harmonic distortion artifacts
•"Staircase" output waveform
•Information loss below 1 LSB

With Dither (Small Signals)

•Smooth noise-like error
•Uncorrelated with signal
•No harmonic artifacts
•Sub-LSB information preserved
•Improved with averaging

Noise-Shaped Dither and Sigma-Delta ADCs

Delta-Sigma (ΣΔ) ADCs take dithering to the extreme—they deliberately use very low resolution (often 1 bit!) but at extremely high oversampling rates. Sophisticated feedback 'noise-shapes' the quantization error, pushing it to high frequencies where it can be filtered out. The result: 24-bit effective resolution from a 1-bit quantizer running at MHz rates.

ADC Architectures

Different applications require different tradeoffs between speed, resolution, power, and cost. Several ADC architectures have evolved to address these varied needs.

Flash ADC (Parallel ADC):

Uses 2^N−1 comparators in parallel, each set to a different threshold
All comparisons happen simultaneously—extremely fast
Speed: Up to 10+ GS/s possible
Resolution: Limited to 6-8 bits (comparator count doubles with each bit)
Applications: Oscilloscopes, radar, ultra-high-speed communications

Successive Approximation Register (SAR) ADC:

Uses binary search: compare to midpoint, halve the range, repeat
N comparisons for N bits (very efficient)
Speed: 100 kS/s to 100 MS/s
Resolution: 8-20 bits common
Applications: Data acquisition, sensor interfaces, general purpose

Pipeline ADC:

Cascades stages, each resolving a few bits
Stages operate in parallel on sequential samples
Speed: 10 MS/s to 1 GS/s
Resolution: 8-16 bits
Applications: Communications, video, imaging

Delta-Sigma (ΣΔ) ADC:

Oversamples at low resolution, uses noise-shaping and digital filtering
Trades speed for resolution through oversampling
Speed: 10 S/s to 10 MS/s (after decimation)
Resolution: 16-24 bits common
Applications: Audio, precision measurement, sensors

ADC Architecture Comparison
Architecture	Speed	Resolution	Power	Best For
Flash	Fastest (10+ GS/s)	Low (6-8 bits)	High	Ultra-high-speed, low resolution
SAR	Medium (100 MS/s)	Mid-High (8-20 bits)	Low	General purpose, low power
Pipeline	Fast (1 GS/s)	Medium (8-16 bits)	Medium	Communications, video
Delta-Sigma	Slow (10 MS/s)	Highest (16-24 bits)	Low-Medium	Precision, audio, sensors
Dual-Slope	Very Slow	High (12-16 bits)	Very Low	Multimeters, lab instruments

The Speed-Resolution-Power Triangle

ADC design involves fundamental tradeoffs: you can optimize for any two of {speed, resolution, power} but rarely all three. High speed at high resolution requires high power. Low power at high resolution means lower speed. Flash ADCs sacrifice resolution for speed. Delta-Sigma ADCs sacrifice speed for resolution. SAR ADCs balance all three for moderate requirements.

Practical ADC Specifications

When selecting an ADC for a communication system, many specifications matter beyond basic resolution and speed.

Static Specifications:

Integral Nonlinearity (INL): Maximum deviation of the actual transfer function from an ideal straight line. Measured in LSB. Causes harmonic distortion.

Differential Nonlinearity (DNL): Deviation of actual step size from ideal 1 LSB. DNL > 1 LSB causes 'missing codes'. Causes intermodulation distortion.

Offset Error: DC shift of the transfer function. Can usually be calibrated out.

Gain Error: Slope deviation from ideal. Can usually be calibrated out.

Dynamic Specifications:

Signal-to-Noise Ratio (SNR): Ratio of signal power to noise power (excluding harmonics). Includes thermal noise, not just quantization noise.

Signal-to-Noise and Distortion (SINAD): Ratio of signal to noise + distortion. The most comprehensive single-number specification.

Effective Number of Bits (ENOB): Bits of an ideal ADC that would give same SINAD: ENOB = (SINAD - 1.76) / 6.02

Spurious-Free Dynamic Range (SFDR): Ratio of signal to the largest spurious component (usually a harmonic). Critical for narrowband systems.

Total Harmonic Distortion (THD): Power in harmonics relative to fundamental. Caused by nonlinearity.

Input Bandwidth: Frequency at which input track-and-hold response is -3dB. Must exceed Nyquist frequency for full-rate operation.

Key Specifications for Communications

•ENOB at signal frequency — Not at DC! Performance degrades at higher frequencies.
•SFDR — Critical for receivers near strong interferers
•Aperture jitter — Limits high-frequency performance regardless of resolution
•Input bandwidth — Must exceed target frequencies with margin
•Latency (pipeline delay) — Number of clock cycles from input to output; matters for feedback systems
•Power consumption — Especially important for battery-powered devices
•Clock requirements — Some ADCs need clean clocks; others include PLLs

Specifications Degrade at High Frequency

ADC datasheets often show impressive specs at low frequencies. Check performance at YOUR frequencies. A 14-bit ADC might achieve 13 ENOB at 1 MHz but only 9 ENOB at 70 MHz due to aperture jitter. Always examine ENOB vs. frequency plots for your target application.

Oversampling and Decimation

Oversampling means sampling at a rate significantly higher than the Nyquist minimum. Combined with decimation (digital filtering and downsampling), this technique offers remarkable benefits.

The Oversampling Ratio:

Oversampling Ratio (OSR) = fs / (2 × fmax)

If fmax = 20 kHz and fs = 2.88 MHz, then OSR = 72.

Benefits of Oversampling:

1. Relaxed Anti-Aliasing Filter:

With 2× oversampling, the anti-alias filter has from f to fs-f to roll off (the whole Nyquist bandwidth). With 64× oversampling, it has from f to 127f—a much gentler, cheaper filter suffices.

2. Reduced Quantization Noise in Band:

Quantization noise power is spread across 0 to fs/2. With higher fs, the same total noise is spread thinner. The noise in the signal bandwidth decreases:

SNR improvement = 10 log₁₀(OSR) dB

64× oversampling gives ~18 dB improvement (~3 bits).

3. Resolution Enhancement:

With noise-shaped oversampling (delta-sigma), each doubling of OSR can add 0.5 bits of effective resolution (first-order shaping) to 2.5 bits (fourth-order shaping).

Decimation:

After oversampling, a digital low-pass filter removes out-of-band noise, then the data rate is reduced (decimated) to the target rate. The digital filter does what the analog anti-alias filter couldn't do perfectly—it has sharp cutoff with flat passband.

Example: CD Audio

Original CD players used 16-bit DACs at 44.1 kHz with complex multi-stage analog filters. Modern players oversample to 352.8 kHz (8×) or higher, use simple analog filters, and rely on digital filtering for precision.

Oversampling Benefits Summary
OSR	Filter Transition Band	Noise Floor Reduction	Equivalent Resolution Gain
2×	fmax to 3fmax	3 dB	~0.5 bits
4×	fmax to 7fmax	6 dB	~1 bit
16×	fmax to 31fmax	12 dB	~2 bits
64×	fmax to 127fmax	18 dB	~3 bits
256×	fmax to 511fmax	24 dB	~4 bits

Software-Defined Radio Relies on Oversampling

SDR receivers deliberately oversample—they capture a wide bandwidth digitally, then use digital filters to select the desired channel. A 100 MHz ADC might sample a 10 MHz channel at 10× oversampling. Digital channelizers then extract the desired signal with perfect selectivity. This flexibility is why SDR has transformed communications.

Summary: Mastering Analog-to-Digital Conversion

We have thoroughly explored analog-to-digital conversion—the critical process that bridges the continuous analog world to the discrete digital domain. Let's consolidate the essential concepts:

Key Takeaways

•ADC involves three steps: sampling, quantization, encoding — Each is distinct and must occur in order with appropriate filtering.
•The Nyquist theorem governs sampling — fs > 2fmax is required for perfect reconstruction; aliasing corrupts frequencies above fs/2.
•Anti-alias filters are essential — Remove out-of-band signals before sampling to prevent irrecoverable aliasing.
•Quantization adds noise proportional to 1 LSB — SQNR = 6.02N + 1.76 dB; each bit adds ~6 dB dynamic range.
•ENOB reflects real-world performance — Look beyond stated resolution to actual SINAD-based effective bits.
•Different architectures suit different needs — Flash for speed, SAR for balance, pipeline for moderate speed/resolution, delta-sigma for precision.
•Oversampling trades speed for resolution — Combined with decimation, it relaxes analog filter requirements and improves SNR.

What's Next:

We've covered the conversion from analog to digital. The next page explores the reverse process: Digital-to-Analog Conversion—how discrete digital samples are reconstructed into continuous analog signals for transmission or output.

The Bridge is Built

You now understand how continuous analog signals enter the digital domain. Sampling captures time information, quantization captures amplitude information, and encoding produces the binary numbers that computers manipulate. This ADC knowledge is foundational for all digital communication systems—from WiFi to 5G to fiber optics.